1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * NXP ls1088a QDS common board device tree source
5 * Copyright 2017-2020 NXP
8 #include "fsl-ls1088a.dtsi"
32 compatible = "simple-mfd";
38 compatible = "mdio-mux-i2creg";
40 #mux-control-cells = <1>;
41 mux-reg-masks = <0x54 0xe0>; // reg 0x54, bits 7:5
42 mdio-parent-bus = <&emdio1>;
49 rgmii_phy1: ethernet-phy@1 {
58 rgmii_phy2: ethernet-phy@2 {
63 emdio1_slot1: mdio@40 { /* I/O Slot #1 */
65 device-name = "emdio1_slot1";
70 emdio1_slot3: mdio@60 { /* I/O Slot #3 */
72 device-name = "emdio1_slot3";
80 compatible = "nxp,pca9547";
91 compatible = "pcf2127-rtc";
101 /* NOR, NAND Flashes and FPGA on board */
102 ranges = <0 0 0x5 0x80000000 0x08000000
103 2 0 0x5 0x30000000 0x00010000
104 3 0 0x5 0x20000000 0x00010000>;
108 #address-cells = <1>;
110 compatible = "cfi-flash";
111 reg = <0x0 0x0 0x8000000>;
117 compatible = "fsl,ifc-nand";
118 #address-cells = <1>;
120 reg = <0x1 0x0 0x10000>;
123 fpga: board-control@3,0 {
124 #address-cells = <1>;
126 compatible = "simple-bus", "fsl,ls1088aqds-fpga",
128 reg = <0x2 0x0 0x0000100>;
131 ranges = <0 2 0 0x100>;
140 #address-cells = <1>;
142 compatible = "jedec,spi-nor";
144 spi-max-frequency = <1000000>; /* input clock */
147 dflash1: sst25wf040b {
148 #address-cells = <1>;
150 compatible = "jedec,spi-nor";
151 spi-max-frequency = <3500000>;
156 #address-cells = <1>;
158 compatible = "jedec,spi-nor";
159 spi-max-frequency = <3500000>;
167 s25fs512s0: flash@0 {
168 #address-cells = <1>;
170 compatible = "jedec,spi-nor";
171 spi-max-frequency = <50000000>;
175 s25fs512s1: flash@1 {
176 #address-cells = <1>;
178 compatible = "jedec,spi-nor";
179 spi-max-frequency = <50000000>;