arch/arm/dts/fsl-ls1088a-qds.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP ls1088a QDS board device tree source
   4  *
   5  * Copyright 2017 NXP
   6  */
   7
   8 /dts-v1/;
   9
  10 #include "fsl-ls1088a.dtsi"
  11
  12 / {
  13         model = "NXP Layerscape 1088a QDS Board";
  14         compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
  15         aliases {
  16                 spi0 = &qspi;
  17                 spi1 = &dspi;
  18         };
  19 };
  20
  21 &i2c0 {
  22         status = "okay";
  23         u-boot,dm-pre-reloc;
  24
  25         i2c-mux@77 {
  26                 compatible = "nxp,pca9547";
  27                 reg = <0x77>;
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 i2c@3 {
  32                         #address-cells = <1>;
  33                         #size-cells = <0>;
  34                         reg = <0x3>;
  35
  36                         rtc@51 {
  37                                 compatible = "pcf2127-rtc";
  38                                 reg = <0x51>;
  39                         };
  40                 };
  41         };
  42 };
  43
  44 &ifc {
  45         #address-cells = <2>;
  46         #size-cells = <1>;
  47         /* NOR, NAND Flashes and FPGA on board */
  48         ranges = <0 0 0x5 0x80000000 0x08000000
  49                         2 0 0x5 0x30000000 0x00010000
  50                         3 0 0x5 0x20000000 0x00010000>;
  51         status = "okay";
  52
  53         nor@0,0 {
  54                 #address-cells = <1>;
  55                 #size-cells = <1>;
  56                 compatible = "cfi-flash";
  57                 reg = <0x0 0x0 0x8000000>;
  58                 bank-width = <2>;
  59                 device-width = <1>;
  60         };
  61
  62         nand@2,0 {
  63                 compatible = "fsl,ifc-nand";
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66                 reg = <0x1 0x0 0x10000>;
  67         };
  68
  69         fpga: board-control@3,0 {
  70                 #address-cells = <1>;
  71                 #size-cells = <1>;
  72                 compatible = "simple-bus", "fsl,ls1088aqds-fpga",
  73                                 "fsl,fpga-qixis";
  74                 reg = <0x2 0x0 0x0000100>;
  75                 bank-width = <1>;
  76                 device-width = <1>;
  77                 ranges = <0 2 0 0x100>;
  78         };
  79 };
  80
  81 &dspi {
  82         bus-num = <0>;
  83         status = "okay";
  84
  85         dflash0: n25q128a {
  86                 #address-cells = <1>;
  87                 #size-cells = <1>;
  88                 compatible = "jedec,spi-nor";
  89                 reg = <0>;
  90                 spi-max-frequency = <1000000>; /* input clock */
  91         };
  92
  93         dflash1: sst25wf040b {
  94                 #address-cells = <1>;
  95                 #size-cells = <1>;
  96                 compatible = "jedec,spi-nor";
  97                 spi-max-frequency = <3500000>;
  98                 reg = <1>;
  99         };
 100
 101         dflash2: en25s64 {
 102                 #address-cells = <1>;
 103                 #size-cells = <1>;
 104                 compatible = "jedec,spi-nor";
 105                 spi-max-frequency = <3500000>;
 106                 reg = <2>;
 107         };
 108 };
 109
 110 &qspi {
 111         status = "okay";
 112
 113         s25fs512s0: flash@0 {
 114                 #address-cells = <1>;
 115                 #size-cells = <1>;
 116                 compatible = "jedec,spi-nor";
 117                 spi-max-frequency = <50000000>;
 118                 reg = <0>;
 119         };
 120
 121         s25fs512s1: flash@1 {
 122                 #address-cells = <1>;
 123                 #size-cells = <1>;
 124                 compatible = "jedec,spi-nor";
 125                 spi-max-frequency = <50000000>;
 126                 reg = <1>;
 127          };
 128 };
 129
 130 &sata {
 131         status = "okay";
 132 };