arch/arm/dts/fsl-ls1043a.dtsi

   1 /*
   2  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
   3  *
   4  * Copyright (C) 2014-2015, Freescale Semiconductor
   5  *
   6  * Mingkai Hu <Mingkai.hu@freescale.com>
   7  *
   8  * SPDX-License-Identifier:    GPL-2.0+ X11
   9  */
  10
  11 /include/ "skeleton64.dtsi"
  12
  13 / {
  14         compatible = "fsl,ls1043a";
  15         interrupt-parent = <&gic>;
  16
  17         sysclk: sysclk {
  18                 compatible = "fixed-clock";
  19                 #clock-cells = <0>;
  20                 clock-frequency = <100000000>;
  21                 clock-output-names = "sysclk";
  22         };
  23
  24         gic: interrupt-controller@1400000 {
  25                 compatible = "arm,gic-400";
  26                 #interrupt-cells = <3>;
  27                 interrupt-controller;
  28                 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
  29                       <0x0 0x1402000 0 0x2000>, /* GICC */
  30                       <0x0 0x1404000 0 0x2000>, /* GICH */
  31                       <0x0 0x1406000 0 0x2000>; /* GICV */
  32                 interrupts = <1 9 0xf08>;
  33         };
  34
  35         soc {
  36                 compatible = "simple-bus";
  37                 #address-cells = <2>;
  38                 #size-cells = <2>;
  39                 ranges;
  40
  41                 clockgen: clocking@1ee1000 {
  42                         compatible = "fsl,ls1043a-clockgen";
  43                         reg = <0x0 0x1ee1000 0x0 0x1000>;
  44                         #clock-cells = <2>;
  45                         clocks = <&sysclk>;
  46                 };
  47
  48                 dspi0: dspi@2100000 {
  49                         compatible = "fsl,vf610-dspi";
  50                         #address-cells = <1>;
  51                         #size-cells = <0>;
  52                         reg = <0x0 0x2100000 0x0 0x10000>;
  53                         interrupts = <0 64 0x4>;
  54                         clock-names = "dspi";
  55                         clocks = <&clockgen 4 0>;
  56                         num-cs = <6>;
  57                         big-endian;
  58                         status = "disabled";
  59                 };
  60
  61                 dspi1: dspi@2110000 {
  62                         compatible = "fsl,vf610-dspi";
  63                         #address-cells = <1>;
  64                         #size-cells = <0>;
  65                         reg = <0x0 0x2110000 0x0 0x10000>;
  66                         interrupts = <0 65 0x4>;
  67                         clock-names = "dspi";
  68                         clocks = <&clockgen 4 0>;
  69                         num-cs = <6>;
  70                         big-endian;
  71                         status = "disabled";
  72                 };
  73
  74                 ifc: ifc@1530000 {
  75                         compatible = "fsl,ifc", "simple-bus";
  76                         reg = <0x0 0x1530000 0x0 0x10000>;
  77                         interrupts = <0 43 0x4>;
  78                 };
  79
  80                 i2c0: i2c@2180000 {
  81                         compatible = "fsl,vf610-i2c";
  82                         #address-cells = <1>;
  83                         #size-cells = <0>;
  84                         reg = <0x0 0x2180000 0x0 0x10000>;
  85                         interrupts = <0 56 0x4>;
  86                         clock-names = "i2c";
  87                         clocks = <&clockgen 4 0>;
  88                         status = "disabled";
  89                 };
  90
  91                 i2c1: i2c@2190000 {
  92                         compatible = "fsl,vf610-i2c";
  93                         #address-cells = <1>;
  94                         #size-cells = <0>;
  95                         reg = <0x0 0x2190000 0x0 0x10000>;
  96                         interrupts = <0 57 0x4>;
  97                         clock-names = "i2c";
  98                         clocks = <&clockgen 4 0>;
  99                         status = "disabled";
 100                 };
 101
 102                 i2c2: i2c@21a0000 {
 103                         compatible = "fsl,vf610-i2c";
 104                         #address-cells = <1>;
 105                         #size-cells = <0>;
 106                         reg = <0x0 0x21a0000 0x0 0x10000>;
 107                         interrupts = <0 58 0x4>;
 108                         clock-names = "i2c";
 109                         clocks = <&clockgen 4 0>;
 110                         status = "disabled";
 111                 };
 112
 113                 i2c3: i2c@21b0000 {
 114                         compatible = "fsl,vf610-i2c";
 115                         #address-cells = <1>;
 116                         #size-cells = <0>;
 117                         reg = <0x0 0x21b0000 0x0 0x10000>;
 118                         interrupts = <0 59 0x4>;
 119                         clock-names = "i2c";
 120                         clocks = <&clockgen 4 0>;
 121                         status = "disabled";
 122                 };
 123
 124                 duart0: serial@21c0500 {
 125                         compatible = "fsl,ns16550", "ns16550a";
 126                         reg = <0x00 0x21c0500 0x0 0x100>;
 127                         interrupts = <0 54 0x4>;
 128                         clocks = <&clockgen 4 0>;
 129                 };
 130
 131                 duart1: serial@21c0600 {
 132                         compatible = "fsl,ns16550", "ns16550a";
 133                         reg = <0x00 0x21c0600 0x0 0x100>;
 134                         interrupts = <0 54 0x4>;
 135                         clocks = <&clockgen 4 0>;
 136                 };
 137
 138                 duart2: serial@21d0500 {
 139                         compatible = "fsl,ns16550", "ns16550a";
 140                         reg = <0x0 0x21d0500 0x0 0x100>;
 141                         interrupts = <0 55 0x4>;
 142                         clocks = <&clockgen 4 0>;
 143                 };
 144
 145                 duart3: serial@21d0600 {
 146                         compatible = "fsl,ns16550", "ns16550a";
 147                         reg = <0x0 0x21d0600 0x0 0x100>;
 148                         interrupts = <0 55 0x4>;
 149                         clocks = <&clockgen 4 0>;
 150                 };
 151
 152                 lpuart0: serial@2950000 {
 153                         compatible = "fsl,ls1021a-lpuart";
 154                         reg = <0x0 0x2950000 0x0 0x1000>;
 155                         interrupts = <0 48 0x4>;
 156                         clocks = <&sysclk>;
 157                         clock-names = "ipg";
 158                         status = "disabled";
 159                 };
 160
 161                 lpuart1: serial@2960000 {
 162                         compatible = "fsl,ls1021a-lpuart";
 163                         reg = <0x0 0x2960000 0x0 0x1000>;
 164                         interrupts = <0 49 0x4>;
 165                         clocks = <&sysclk>;
 166                         clock-names = "ipg";
 167                         status = "disabled";
 168                 };
 169
 170                 lpuart2: serial@2970000 {
 171                         compatible = "fsl,ls1021a-lpuart";
 172                         reg = <0x0 0x2970000 0x0 0x1000>;
 173                         interrupts = <0 50 0x4>;
 174                         clock-names = "ipg";
 175                         clocks = <&sysclk>;
 176                         status = "disabled";
 177                 };
 178
 179                 lpuart3: serial@2980000 {
 180                         compatible = "fsl,ls1021a-lpuart";
 181                         reg = <0x0 0x2980000 0x0 0x1000>;
 182                         interrupts = <0 51 0x4>;
 183                         clocks = <&sysclk>;
 184                         clock-names = "ipg";
 185                         status = "disabled";
 186                 };
 187
 188                 lpuart4: serial@2990000 {
 189                         compatible = "fsl,ls1021a-lpuart";
 190                         reg = <0x0 0x2990000 0x0 0x1000>;
 191                         interrupts = <0 52 0x4>;
 192                         clocks = <&sysclk>;
 193                         clock-names = "ipg";
 194                         status = "disabled";
 195                 };
 196
 197                 lpuart5: serial@29a0000 {
 198                         compatible = "fsl,ls1021a-lpuart";
 199                         reg = <0x0 0x29a0000 0x0 0x1000>;
 200                         interrupts = <0 53 0x4>;
 201                         clocks = <&sysclk>;
 202                         clock-names = "ipg";
 203                         status = "disabled";
 204                 };
 205                 qspi: quadspi@1550000 {
 206                         compatible = "fsl,vf610-qspi";
 207                         #address-cells = <1>;
 208                         #size-cells = <0>;
 209                         reg = <0x0 0x1550000 0x0 0x10000>,
 210                                 <0x0 0x40000000 0x0 0x4000000>;
 211                         reg-names = "QuadSPI", "QuadSPI-memory";
 212                         num-cs = <2>;
 213                         big-endian;
 214                         status = "disabled";
 215                 };
 216
 217                 usb0: usb3@2f00000 {
 218                         compatible = "fsl,layerscape-dwc3";
 219                         reg = <0x0 0x2f00000 0x0 0x10000>;
 220                         interrupts = <0 60 0x4>;
 221                         dr_mode = "host";
 222                 };
 223
 224                 usb1: usb3@3000000 {
 225                         compatible = "fsl,layerscape-dwc3";
 226                         reg = <0x0 0x3000000 0x0 0x10000>;
 227                         interrupts = <0 61 0x4>;
 228                         dr_mode = "host";
 229                 };
 230
 231                 usb2: usb3@3100000 {
 232                         compatible = "fsl,layerscape-dwc3";
 233                         reg = <0x0 0x3100000 0x0 0x10000>;
 234                         interrupts = <0 63 0x4>;
 235                         dr_mode = "host";
 236                 };
 237
 238                 pcie@3400000 {
 239                         compatible = "fsl,ls-pcie", "snps,dw-pcie";
 240                         reg = <0x00 0x03400000 0x0 0x10000   /* dbi registers */
 241                                0x00 0x03410000 0x0 0x10000   /* lut registers */
 242                                0x40 0x00000000 0x0 0x20000>; /* configuration space */
 243                         reg-names = "dbi", "lut", "config";
 244                         big-endian;
 245                         #address-cells = <3>;
 246                         #size-cells = <2>;
 247                         device_type = "pci";
 248                         bus-range = <0x0 0xff>;
 249                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000   /* downstream I/O */
 250                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 251                 };
 252
 253                 pcie@3500000 {
 254                         compatible = "fsl,ls-pcie", "snps,dw-pcie";
 255                         reg = <0x00 0x03500000 0x0 0x10000   /* dbi registers */
 256                                0x00 0x03510000 0x0 0x10000   /* lut registers */
 257                                0x48 0x00000000 0x0 0x20000>; /* configuration space */
 258                         reg-names = "dbi", "lut", "config";
 259                         big-endian;
 260                         #address-cells = <3>;
 261                         #size-cells = <2>;
 262                         device_type = "pci";
 263                         num-lanes = <2>;
 264                         bus-range = <0x0 0xff>;
 265                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000   /* downstream I/O */
 266                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 267                 };
 268
 269                 pcie@3600000 {
 270                         compatible = "fsl,ls-pcie", "snps,dw-pcie";
 271                         reg = <0x00 0x03600000 0x0 0x10000   /* dbi registers */
 272                                0x00 0x03610000 0x0 0x10000   /* lut registers */
 273                                0x50 0x00000000 0x0 0x20000>; /* configuration space */
 274                         reg-names = "dbi", "lut", "config";
 275                         big-endian;
 276                         #address-cells = <3>;
 277                         #size-cells = <2>;
 278                         device_type = "pci";
 279                         bus-range = <0x0 0xff>;
 280                         ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000   /* downstream I/O */
 281                                   0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 282                 };
 283         };
 284 };