1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright (C) 2015, Freescale Semiconductor
7 * Mingkai Hu <Mingkai.hu@freescale.com>
10 /include/ "fsl-ls1043a.dtsi"
13 model = "LS1043A QDS Board";
27 compatible = "jedec,spi-nor";
28 spi-max-frequency = <1000000>; /* input clock */
34 dflash1: sst25wf040b {
37 compatible = "jedec,spi-nor";
38 spi-max-frequency = <3500000>;
47 compatible = "jedec,spi-nor";
48 spi-max-frequency = <3500000>;
61 compatible = "jedec,spi-nor";
62 spi-max-frequency = <50000000>;
70 compatible = "philips,pca9547";
81 compatible = "dallas,ds3232";
84 interrupts = <0 150 0x4>;
94 compatible = "ti,ina220";
96 shunt-resistor = <1000>;
100 compatible = "ti,ina220";
102 shunt-resistor = <1000>;
107 #address-cells = <1>;
112 compatible = "at24,24c512";
117 compatible = "at24,24c512";
122 compatible = "adt7461a";
130 #address-cells = <2>;
132 /* NOR, NAND Flashes and FPGA on board */
133 ranges = <0x0 0x0 0x0 0x60000000 0x08000000
134 0x1 0x0 0x0 0x7e800000 0x00010000
135 0x2 0x0 0x0 0x7fb00000 0x00000100>;
139 #address-cells = <1>;
141 compatible = "cfi-flash";
142 reg = <0x0 0x0 0x8000000>;
148 compatible = "fsl,ifc-nand";
149 #address-cells = <1>;
151 reg = <0x1 0x0 0x10000>;
154 fpga: board-control@2,0 {
155 #address-cells = <1>;
157 compatible = "simple-bus";
158 reg = <0x2 0x0 0x0000100>;
161 ranges = <0 2 0 0x100>;