1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright (C) 2015, Freescale Semiconductor
7 * Mingkai Hu <Mingkai.hu@freescale.com>
10 /include/ "fsl-ls1043a.dtsi"
13 model = "LS1043A QDS Board";
27 compatible = "jedec,spi-nor";
28 spi-max-frequency = <1000000>; /* input clock */
34 dflash1: sst25wf040b {
37 compatible = "jedec,spi-nor";
38 spi-max-frequency = <3500000>;
47 compatible = "jedec,spi-nor";
48 spi-max-frequency = <3500000>;
59 qflash0: s25fl128s@0 {
62 compatible = "jedec,spi-nor";
63 spi-max-frequency = <20000000>;
71 compatible = "philips,pca9547";
82 compatible = "dallas,ds3232";
85 interrupts = <0 150 0x4>;
95 compatible = "ti,ina220";
97 shunt-resistor = <1000>;
101 compatible = "ti,ina220";
103 shunt-resistor = <1000>;
108 #address-cells = <1>;
113 compatible = "at24,24c512";
118 compatible = "at24,24c512";
123 compatible = "adt7461a";
131 #address-cells = <2>;
133 /* NOR, NAND Flashes and FPGA on board */
134 ranges = <0x0 0x0 0x0 0x60000000 0x08000000
135 0x1 0x0 0x0 0x7e800000 0x00010000
136 0x2 0x0 0x0 0x7fb00000 0x00000100>;
140 #address-cells = <1>;
142 compatible = "cfi-flash";
143 reg = <0x0 0x0 0x8000000>;
149 compatible = "fsl,ifc-nand";
150 #address-cells = <1>;
152 reg = <0x1 0x0 0x10000>;
155 fpga: board-control@2,0 {
156 #address-cells = <1>;
158 compatible = "simple-bus";
159 reg = <0x2 0x0 0x0000100>;
162 ranges = <0 2 0 0x100>;