arch/arm/dts/fsl-ls1012a.dtsi

   1 /*
   2  * Copyright 2016 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /include/ "skeleton64.dtsi"
   8
   9 / {
  10         compatible = "fsl,ls1012a";
  11         interrupt-parent = <&gic>;
  12
  13         sysclk: sysclk {
  14                 compatible = "fixed-clock";
  15                 #clock-cells = <0>;
  16                 clock-frequency = <100000000>;
  17                 clock-output-names = "sysclk";
  18         };
  19
  20         gic: interrupt-controller@1400000 {
  21                 compatible = "arm,gic-400";
  22                 #interrupt-cells = <3>;
  23                 interrupt-controller;
  24                 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
  25                       <0x0 0x1402000 0 0x2000>, /* GICC */
  26                       <0x0 0x1404000 0 0x2000>, /* GICH */
  27                       <0x0 0x1406000 0 0x2000>; /* GICV */
  28                 interrupts = <1 9 0xf08>;
  29         };
  30
  31         soc {
  32                 compatible = "simple-bus";
  33                 #address-cells = <2>;
  34                 #size-cells = <2>;
  35                 ranges;
  36
  37                 clockgen: clocking@1ee1000 {
  38                         compatible = "fsl,ls1012a-clockgen";
  39                         reg = <0x0 0x1ee1000 0x0 0x1000>;
  40                         #clock-cells = <2>;
  41                         clocks = <&sysclk>;
  42                 };
  43
  44                 dspi0: dspi@2100000 {
  45                         compatible = "fsl,vf610-dspi";
  46                         #address-cells = <1>;
  47                         #size-cells = <0>;
  48                         reg = <0x0 0x2100000 0x0 0x10000>;
  49                         interrupts = <0 64 0x4>;
  50                         clock-names = "dspi";
  51                         clocks = <&clockgen 4 0>;
  52                         num-cs = <6>;
  53                         big-endian;
  54                         status = "disabled";
  55                 };
  56
  57
  58                 i2c0: i2c@2180000 {
  59                         compatible = "fsl,vf610-i2c";
  60                         #address-cells = <1>;
  61                         #size-cells = <0>;
  62                         reg = <0x0 0x2180000 0x0 0x10000>;
  63                         interrupts = <0 56 0x4>;
  64                         clock-names = "i2c";
  65                         clocks = <&clockgen 4 0>;
  66                         status = "disabled";
  67                 };
  68
  69                 i2c1: i2c@2190000 {
  70                         compatible = "fsl,vf610-i2c";
  71                         #address-cells = <1>;
  72                         #size-cells = <0>;
  73                         reg = <0x0 0x2190000 0x0 0x10000>;
  74                         interrupts = <0 57 0x4>;
  75                         clock-names = "i2c";
  76                         clocks = <&clockgen 4 0>;
  77                         status = "disabled";
  78                 };
  79
  80                 duart0: serial@21c0500 {
  81                         compatible = "fsl,ns16550", "ns16550a";
  82                         reg = <0x00 0x21c0500 0x0 0x100>;
  83                         interrupts = <0 54 0x4>;
  84                         clocks = <&clockgen 4 0>;
  85                 };
  86
  87                 duart1: serial@21c0600 {
  88                         compatible = "fsl,ns16550", "ns16550a";
  89                         reg = <0x00 0x21c0600 0x0 0x100>;
  90                         interrupts = <0 54 0x4>;
  91                         clocks = <&clockgen 4 0>;
  92                 };
  93
  94                 qspi: quadspi@1550000 {
  95                         compatible = "fsl,vf610-qspi";
  96                         #address-cells = <1>;
  97                         #size-cells = <0>;
  98                         reg = <0x0 0x1550000 0x0 0x10000>,
  99                                 <0x0 0x40000000 0x0 0x4000000>;
 100                         reg-names = "QuadSPI", "QuadSPI-memory";
 101                         num-cs = <2>;
 102                         big-endian;
 103                         status = "disabled";
 104                 };
 105
 106         };
 107 };