arch/arm/dts/fsl-imx8qxp-mek.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2018 NXP
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "fsl-imx8qxp.dtsi"
   9
  10 / {
  11         model = "Freescale i.MX8QXP MEK";
  12         compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
  13
  14         chosen {
  15                 bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
  16                 stdout-path = &lpuart0;
  17         };
  18
  19         reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
  20                 compatible = "regulator-fixed";
  21                 regulator-name = "SD1_SPWR";
  22                 regulator-min-microvolt = <3000000>;
  23                 regulator-max-microvolt = <3000000>;
  24                 gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
  25                 off-on-delay = <3480>;
  26                 enable-active-high;
  27         };
  28 };
  29
  30 &iomuxc {
  31         pinctrl-names = "default";
  32         pinctrl-0 = <&pinctrl_hog>;
  33
  34         imx8qxp-mek {
  35                 pinctrl_hog: hoggrp {
  36                         fsl,pins = <
  37                                 SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0       0x0600004c
  38                                 SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD  0x000514a0
  39                         >;
  40                 };
  41
  42                 pinctrl_ioexp_rst: ioexp-rst-grp {
  43                         fsl,pins = <
  44                                 SC_P_SPI2_SDO_LSIO_GPIO1_IO01   0x06000021
  45                         >;
  46                 };
  47
  48                 pinctrl_fec1: fec1grp {
  49                         fsl,pins = <
  50                                 SC_P_ENET0_MDC_CONN_ENET0_MDC                   0x06000048
  51                                 SC_P_ENET0_MDIO_CONN_ENET0_MDIO                 0x06000048
  52                                 SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048
  53                                 SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC       0x06000048
  54                                 SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0     0x06000048
  55                                 SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1     0x06000048
  56                                 SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2     0x06000048
  57                                 SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3     0x06000048
  58                                 SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC       0x06000048
  59                                 SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048
  60                                 SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0     0x06000048
  61                                 SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1     0x06000048
  62                                 SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2     0x06000048
  63                                 SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3     0x06000048
  64                         >;
  65                 };
  66
  67                 pinctrl_fec2: fec2grp {
  68                         fsl,pins = <
  69                                 SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL         0x06000048
  70                                 SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC             0x06000048
  71                                 SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0        0x06000048
  72                                 SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1        0x06000048
  73                                 SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2            0x06000048
  74                                 SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3           0x06000048
  75                                 SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC             0x06000048
  76                                 SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL          0x06000048
  77                                 SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0            0x06000048
  78                                 SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1        0x06000048
  79                                 SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2        0x06000048
  80                                 SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3            0x06000048
  81                         >;
  82                 };
  83
  84                 pinctrl_lpi2c1: lpi2c1grp {
  85                         fsl,pins = <
  86                                 SC_P_USB_SS3_TC1_ADMA_I2C1_SCL  0x06000021
  87                                 SC_P_USB_SS3_TC3_ADMA_I2C1_SDA  0x06000021
  88                         >;
  89                 };
  90
  91                 pinctrl_lpuart0: lpuart0grp {
  92                         fsl,pins = <
  93                                 SC_P_UART0_RX_ADMA_UART0_RX     0x06000020
  94                                 SC_P_UART0_TX_ADMA_UART0_TX     0x06000020
  95                         >;
  96                 };
  97
  98                 pinctrl_usdhc1: usdhc1grp {
  99                         fsl,pins = <
 100                                 SC_P_EMMC0_CLK_CONN_EMMC0_CLK           0x06000041
 101                                 SC_P_EMMC0_CMD_CONN_EMMC0_CMD           0x00000021
 102                                 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0       0x00000021
 103                                 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1       0x00000021
 104                                 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2       0x00000021
 105                                 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3       0x00000021
 106                                 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4       0x00000021
 107                                 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000021
 108                                 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000021
 109                                 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000021
 110                                 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x00000041
 111                         >;
 112                 };
 113
 114                 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 115                         fsl,pins = <
 116                                 SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19     0x00000021
 117                                 SC_P_USDHC1_WP_LSIO_GPIO4_IO21          0x00000021
 118                                 SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22        0x00000021
 119                         >;
 120                 };
 121
 122                 pinctrl_usdhc2: usdhc2grp {
 123                         fsl,pins = <
 124                                 SC_P_USDHC1_CLK_CONN_USDHC1_CLK         0x06000041
 125                                 SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x00000021
 126                                 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x00000021
 127                                 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x00000021
 128                                 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x00000021
 129                                 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x00000021
 130                                 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
 131                         >;
 132                 };
 133         };
 134 };
 135
 136 &A35_0 {
 137         u-boot,dm-pre-reloc;
 138 };
 139
 140 &lpuart0 {
 141         pinctrl-names = "default";
 142         pinctrl-0 = <&pinctrl_lpuart0>;
 143         status = "okay";
 144 };
 145
 146 &i2c1 {
 147         clock-frequency = <100000>;
 148         pinctrl-names = "default";
 149         pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
 150         status = "okay";
 151
 152         i2cswitch@71 {
 153                 compatible = "nxp,pca9646";
 154                 reg = <0x71>;
 155                 #address-cells = <1>;
 156                 #size-cells = <0>;
 157                 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 158
 159                 bb_i2c1: i2c@0 {
 160                         #address-cells = <1>;
 161                         #size-cells = <0>;
 162                         reg = <0x0>;
 163                 };
 164
 165                 mfi_i2c1: i2c@1 {
 166                         #address-cells = <1>;
 167                         #size-cells = <0>;
 168                         reg = <0x1>;
 169                 };
 170
 171                 i2cexp1_i2c1: i2c@2 {
 172                         #address-cells = <1>;
 173                         #size-cells = <0>;
 174                         reg = <0x2>;
 175                 };
 176
 177                 i2cexp2_i2c1: i2c@3 {
 178                         #address-cells = <1>;
 179                         #size-cells = <0>;
 180                         reg = <0x3>;
 181
 182                         pca9557_a: gpio@1a {
 183                                 compatible = "nxp,pca9557";
 184                                 reg = <0x1a>;
 185                                 gpio-controller;
 186                                 #gpio-cells = <2>;
 187                         };
 188                         pca9557_b: gpio@1d {
 189                                 compatible = "nxp,pca9557";
 190                                 reg = <0x1d>;
 191                                 gpio-controller;
 192                                 #gpio-cells = <2>;
 193                         };
 194                 };
 195         };
 196 };
 197
 198 &usdhc1 {
 199         pinctrl-names = "default";
 200         pinctrl-0 = <&pinctrl_usdhc1>;
 201         bus-width = <8>;
 202         non-removable;
 203         status = "okay";
 204 };
 205
 206 &usdhc2 {
 207         pinctrl-names = "default";
 208         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 209         bus-width = <4>;
 210         cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 211         wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
 212         vmmc-supply = <&reg_usdhc2_vmmc>;
 213         status = "okay";
 214 };
 215
 216 &fec1 {
 217         pinctrl-names = "default";
 218         pinctrl-0 = <&pinctrl_fec1>;
 219         phy-mode = "rgmii";
 220         phy-handle = <&ethphy0>;
 221         fsl,ar8031-phy-fixup;
 222         fsl,magic-packet;
 223         status = "okay";
 224         phy-reset-gpios = <&pca9557_a 4 GPIO_ACTIVE_LOW>;
 225         phy-reset-duration = <10>;
 226
 227         mdio {
 228                 #address-cells = <1>;
 229                 #size-cells = <0>;
 230
 231                 ethphy0: ethernet-phy@0 {
 232                         compatible = "ethernet-phy-ieee802.3-c22";
 233                         reg = <0>;
 234                 };
 235                 ethphy1: ethernet-phy@1 {
 236                         compatible = "ethernet-phy-ieee802.3-c22";
 237                         reg = <1>;
 238                 };
 239         };
 240 };