arch/arm/dts/fsl-imx8qm.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include "fsl-imx8-ca53.dtsi"
   8 #include <dt-bindings/clock/imx8qm-clock.h>
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/soc/imx_rsrc.h>
  11 #include <dt-bindings/soc/imx8_pd.h>
  12 #include <dt-bindings/pinctrl/pads-imx8qm.h>
  13 #include <dt-bindings/gpio/gpio.h>
  14
  15 / {
  16         compatible = "fsl,imx8qm";
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 ethernet0 = &fec1;
  23                 ethernet1 = &fec2;
  24                 serial0 = &lpuart0;
  25                 mmc0 = &usdhc1;
  26                 mmc1 = &usdhc2;
  27                 mmc2 = &usdhc3;
  28         };
  29
  30         memory@80000000 {
  31                 device_type = "memory";
  32                 reg = <0x00000000 0x80000000 0 0x40000000>;
  33                       /* DRAM space - 1, size : 1 GB DRAM */
  34         };
  35
  36         gic: interrupt-controller@51a00000 {
  37                 compatible = "arm,gic-v3";
  38                 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
  39                       <0x0 0x51b00000 0 0xC0000>, /* GICR */
  40                       <0x0 0x52000000 0 0x2000>,  /* GICC */
  41                       <0x0 0x52010000 0 0x1000>,  /* GICH */
  42                       <0x0 0x52020000 0 0x20000>; /* GICV */
  43                 #interrupt-cells = <3>;
  44                 interrupt-controller;
  45                 interrupts = <GIC_PPI 9
  46                         (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
  47                 interrupt-parent = <&gic>;
  48         };
  49
  50         mu: mu@5d1c0000 {
  51                 compatible = "fsl,imx8-mu";
  52                 reg = <0x0 0x5d1c0000 0x0 0x10000>;
  53                 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
  54                 interrupt-parent = <&gic>;
  55                 fsl,scu_ap_mu_id = <0>;
  56                 status = "okay";
  57
  58                 clk: clk {
  59                         compatible = "fsl,imx8qm-clk";
  60                         #clock-cells = <1>;
  61                 };
  62
  63                 iomuxc: iomuxc {
  64                         compatible = "fsl,imx8qm-iomuxc";
  65                 };
  66         };
  67
  68         imx8qm-pm {
  69                 compatible = "simple-bus";
  70                 #address-cells = <1>;
  71                 #size-cells = <0>;
  72
  73                 pd_lsio: PD_LSIO {
  74                         compatible = "nxp,imx8-pd";
  75                         reg = <SC_R_LAST>;
  76                         #power-domain-cells = <0>;
  77                         #address-cells = <1>;
  78                         #size-cells = <0>;
  79
  80                         pd_lsio_gpio0: PD_LSIO_GPIO_0 {
  81                                 reg = <SC_R_GPIO_0>;
  82                                 #power-domain-cells = <0>;
  83                                 power-domains = <&pd_lsio>;
  84                         };
  85                         pd_lsio_gpio1: PD_LSIO_GPIO_1 {
  86                                 reg = <SC_R_GPIO_1>;
  87                                 #power-domain-cells = <0>;
  88                                 power-domains = <&pd_lsio>;
  89                         };
  90                         pd_lsio_gpio2: PD_LSIO_GPIO_2 {
  91                                 reg = <SC_R_GPIO_2>;
  92                                 #power-domain-cells = <0>;
  93                                 power-domains = <&pd_lsio>;
  94                         };
  95                         pd_lsio_gpio3: PD_LSIO_GPIO_3 {
  96                                 reg = <SC_R_GPIO_3>;
  97                                 #power-domain-cells = <0>;
  98                                 power-domains = <&pd_lsio>;
  99                         };
 100                         pd_lsio_gpio4: PD_LSIO_GPIO_4 {
 101                                 reg = <SC_R_GPIO_4>;
 102                                 #power-domain-cells = <0>;
 103                                 power-domains = <&pd_lsio>;
 104                         };
 105                         pd_lsio_gpio5: PD_LSIO_GPIO_5{
 106                                 reg = <SC_R_GPIO_5>;
 107                                 #power-domain-cells = <0>;
 108                                 power-domains = <&pd_lsio>;
 109                         };
 110                         pd_lsio_gpio6:PD_LSIO_GPIO_6 {
 111                                 reg = <SC_R_GPIO_6>;
 112                                 #power-domain-cells = <0>;
 113                                 power-domains = <&pd_lsio>;
 114                         };
 115                         pd_lsio_gpio7: PD_LSIO_GPIO_7 {
 116                                 reg = <SC_R_GPIO_7>;
 117                                 #power-domain-cells = <0>;
 118                                 power-domains = <&pd_lsio>;
 119                         };
 120                 };
 121
 122                 pd_conn: PD_CONN {
 123                         compatible = "nxp,imx8-pd";
 124                         reg = <SC_R_LAST>;
 125                         #power-domain-cells = <0>;
 126                         #address-cells = <1>;
 127                         #size-cells = <0>;
 128
 129                         pd_conn_sdch0: PD_CONN_SDHC_0 {
 130                                 reg = <SC_R_SDHC_0>;
 131                                 #power-domain-cells = <0>;
 132                                 power-domains = <&pd_conn>;
 133                         };
 134                         pd_conn_sdch1: PD_CONN_SDHC_1 {
 135                                 reg = <SC_R_SDHC_1>;
 136                                 #power-domain-cells = <0>;
 137                                 power-domains = <&pd_conn>;
 138                         };
 139                         pd_conn_sdch2: PD_CONN_SDHC_2 {
 140                                 reg = <SC_R_SDHC_2>;
 141                                 #power-domain-cells = <0>;
 142                                 power-domains = <&pd_conn>;
 143                         };
 144                         pd_conn_enet0: PD_CONN_ENET_0 {
 145                                 reg = <SC_R_ENET_0>;
 146                                 #power-domain-cells = <0>;
 147                                 power-domains = <&pd_conn>;
 148                                 wakeup-irq = <258>;
 149                         };
 150                         pd_conn_enet1: PD_CONN_ENET_1 {
 151                                 reg = <SC_R_ENET_1>;
 152                                 #power-domain-cells = <0>;
 153                                 power-domains = <&pd_conn>;
 154                                 fsl,wakeup_irq = <262>;
 155                         };
 156                 };
 157
 158                 pd_dma: PD_DMA {
 159                         compatible = "nxp,imx8-pd";
 160                         reg = <SC_R_LAST>;
 161                         #power-domain-cells = <0>;
 162                         #address-cells = <1>;
 163                         #size-cells = <0>;
 164
 165                         pd_dma_lpi2c0: PD_DMA_I2C_0 {
 166                                 reg = <SC_R_I2C_0>;
 167                                 #power-domain-cells = <0>;
 168                                 power-domains = <&pd_dma>;
 169                         };
 170                         pd_dma_lpi2c1: PD_DMA_I2C_1 {
 171                                 reg = <SC_R_I2C_1>;
 172                                 #power-domain-cells = <0>;
 173                                 power-domains = <&pd_dma>;
 174                         };
 175                         pd_dma_lpi2c2:PD_DMA_I2C_2 {
 176                                 reg = <SC_R_I2C_2>;
 177                                 #power-domain-cells = <0>;
 178                                 power-domains = <&pd_dma>;
 179                         };
 180                         pd_dma_lpi2c3: PD_DMA_I2C_3 {
 181                                 reg = <SC_R_I2C_3>;
 182                                 #power-domain-cells = <0>;
 183                                 power-domains = <&pd_dma>;
 184                         };
 185                         pd_dma_lpi2c4: PD_DMA_I2C_4 {
 186                                 reg = <SC_R_I2C_4>;
 187                                 #power-domain-cells = <0>;
 188                                 power-domains = <&pd_dma>;
 189                         };
 190                         pd_dma_lpuart0: PD_DMA_UART0 {
 191                                 reg = <SC_R_UART_0>;
 192                                 #power-domain-cells = <0>;
 193                                 power-domains = <&pd_dma>;
 194                                 wakeup-irq = <345>;
 195                         };
 196                 };
 197         };
 198
 199         gpio0: gpio@5d080000 {
 200                 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
 201                 reg = <0x0 0x5d080000 0x0 0x10000>;
 202                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 203                 gpio-controller;
 204                 #gpio-cells = <2>;
 205                 power-domains = <&pd_lsio_gpio0>;
 206                 interrupt-controller;
 207                 #interrupt-cells = <2>;
 208         };
 209
 210         gpio1: gpio@5d090000 {
 211                 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
 212                 reg = <0x0 0x5d090000 0x0 0x10000>;
 213                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 214                 gpio-controller;
 215                 #gpio-cells = <2>;
 216                 power-domains = <&pd_lsio_gpio1>;
 217                 interrupt-controller;
 218                 #interrupt-cells = <2>;
 219         };
 220
 221         gpio2: gpio@5d0a0000 {
 222                 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
 223                 reg = <0x0 0x5d0a0000 0x0 0x10000>;
 224                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 225                 gpio-controller;
 226                 #gpio-cells = <2>;
 227                 power-domains = <&pd_lsio_gpio2>;
 228                 interrupt-controller;
 229                 #interrupt-cells = <2>;
 230         };
 231
 232         gpio3: gpio@5d0b0000 {
 233                 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
 234                 reg = <0x0 0x5d0b0000 0x0 0x10000>;
 235                 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 236                 gpio-controller;
 237                 #gpio-cells = <2>;
 238                 power-domains = <&pd_lsio_gpio3>;
 239                 interrupt-controller;
 240                 #interrupt-cells = <2>;
 241         };
 242
 243         gpio4: gpio@5d0c0000 {
 244                 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
 245                 reg = <0x0 0x5d0c0000 0x0 0x10000>;
 246                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 247                 gpio-controller;
 248                 #gpio-cells = <2>;
 249                 power-domains = <&pd_lsio_gpio4>;
 250                 interrupt-controller;
 251                 #interrupt-cells = <2>;
 252         };
 253
 254         gpio5: gpio@5d0d0000 {
 255                 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
 256                 reg = <0x0 0x5d0d0000 0x0 0x10000>;
 257                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 258                 gpio-controller;
 259                 #gpio-cells = <2>;
 260                 power-domains = <&pd_lsio_gpio5>;
 261                 interrupt-controller;
 262                 #interrupt-cells = <2>;
 263         };
 264
 265         gpio6: gpio@5d0e0000 {
 266                 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
 267                 reg = <0x0 0x5d0e0000 0x0 0x10000>;
 268                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 269                 gpio-controller;
 270                 #gpio-cells = <2>;
 271                 power-domains = <&pd_lsio_gpio6>;
 272                 interrupt-controller;
 273                 #interrupt-cells = <2>;
 274         };
 275
 276         gpio7: gpio@5d0f0000 {
 277                 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
 278                 reg = <0x0 0x5d0f0000 0x0 0x10000>;
 279                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 280                 gpio-controller;
 281                 #gpio-cells = <2>;
 282                 power-domains = <&pd_lsio_gpio7>;
 283                 interrupt-controller;
 284                 #interrupt-cells = <2>;
 285         };
 286
 287         lpuart0: serial@5a060000 {
 288                 compatible = "fsl,imx8qm-lpuart";
 289                 reg = <0x0 0x5a060000 0x0 0x1000>;
 290                 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
 291                 clocks = <&clk IMX8QM_UART0_CLK>,
 292                          <&clk IMX8QM_UART0_IPG_CLK>;
 293                 clock-names = "per", "ipg";
 294                 assigned-clocks = <&clk IMX8QM_UART0_CLK>;
 295                 assigned-clock-rates = <80000000>;
 296                 power-domains = <&pd_dma_lpuart0>;
 297                 status = "disabled";
 298         };
 299
 300         usdhc1: usdhc@5b010000 {
 301                 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
 302                 interrupt-parent = <&gic>;
 303                 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
 304                 reg = <0x0 0x5b010000 0x0 0x10000>;
 305                 clocks = <&clk IMX8QM_SDHC0_IPG_CLK>,
 306                          <&clk IMX8QM_SDHC0_CLK>,
 307                          <&clk IMX8QM_CLK_DUMMY>;
 308                 clock-names = "ipg", "per", "ahb";
 309                 assigned-clocks = <&clk IMX8QM_SDHC0_DIV>;
 310                 assigned-clock-rates = <400000000>;
 311                 power-domains = <&pd_conn_sdch0>;
 312                 fsl,tuning-start-tap = <20>;
 313                 fsl,tuning-step= <2>;
 314                 status = "disabled";
 315         };
 316
 317         usdhc2: usdhc@5b020000 {
 318                 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
 319                 interrupt-parent = <&gic>;
 320                 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
 321                 reg = <0x0 0x5b020000 0x0 0x10000>;
 322                 clocks = <&clk IMX8QM_SDHC1_IPG_CLK>,
 323                          <&clk IMX8QM_SDHC1_CLK>,
 324                          <&clk IMX8QM_CLK_DUMMY>;
 325                 clock-names = "ipg", "per", "ahb";
 326                 assigned-clocks = <&clk IMX8QM_SDHC1_DIV>;
 327                 assigned-clock-rates = <200000000>;
 328                 power-domains = <&pd_conn_sdch1>;
 329                 fsl,tuning-start-tap = <20>;
 330                 fsl,tuning-step= <2>;
 331                 status = "disabled";
 332         };
 333
 334         usdhc3: usdhc@5b030000 {
 335                 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
 336                 interrupt-parent = <&gic>;
 337                 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
 338                 reg = <0x0 0x5b030000 0x0 0x10000>;
 339                 clocks = <&clk IMX8QM_SDHC2_IPG_CLK>,
 340                          <&clk IMX8QM_SDHC2_CLK>,
 341                          <&clk IMX8QM_CLK_DUMMY>;
 342                 clock-names = "ipg", "per", "ahb";
 343                 assigned-clocks = <&clk IMX8QM_SDHC2_DIV>;
 344                 assigned-clock-rates = <200000000>;
 345                 power-domains = <&pd_conn_sdch2>;
 346                 status = "disabled";
 347         };
 348
 349         fec1: ethernet@5b040000 {
 350                 compatible = "fsl,imx8qm-fec", "fsl,imx7d-fec";
 351                 reg = <0x0 0x5b040000 0x0 0x10000>;
 352                 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 353                              <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 354                              <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 355                              <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
 356                 clocks = <&clk IMX8QM_ENET0_IPG_CLK>,
 357                          <&clk IMX8QM_ENET0_AHB_CLK>,
 358                          <&clk IMX8QM_ENET0_RGMII_TX_CLK>,
 359                          <&clk IMX8QM_ENET0_PTP_CLK>,
 360                          <&clk IMX8QM_ENET0_TX_CLK>;
 361                 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp",
 362                               "enet_2x_txclk";
 363                 assigned-clocks = <&clk IMX8QM_ENET0_ROOT_DIV>,
 364                                   <&clk IMX8QM_ENET0_REF_DIV>;
 365                 assigned-clock-rates = <250000000>, <125000000>;
 366                 fsl,num-tx-queues=<3>;
 367                 fsl,num-rx-queues=<3>;
 368                 fsl,wakeup_irq = <0>;
 369                 power-domains = <&pd_conn_enet0>;
 370                 status = "disabled";
 371         };
 372
 373         fec2: ethernet@5b050000 {
 374                 compatible = "fsl,imx8qm-fec", "fsl,imx7d-fec";
 375                 reg = <0x0 0x5b050000 0x0 0x10000>;
 376                 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 377                              <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
 378                              <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 379                              <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
 380                 clocks = <&clk IMX8QM_ENET1_IPG_CLK>,
 381                          <&clk IMX8QM_ENET1_AHB_CLK>,
 382                          <&clk IMX8QM_ENET1_RGMII_TX_CLK>,
 383                          <&clk IMX8QM_ENET1_PTP_CLK>,
 384                          <&clk IMX8QM_ENET1_TX_CLK>;
 385                 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp",
 386                               "enet_2x_txclk";
 387                 assigned-clocks = <&clk IMX8QM_ENET1_ROOT_DIV>,
 388                                   <&clk IMX8QM_ENET1_REF_DIV>;
 389                 assigned-clock-rates = <250000000>, <125000000>;
 390                 fsl,num-tx-queues=<3>;
 391                 fsl,num-rx-queues=<3>;
 392                 fsl,wakeup_irq = <0>;
 393                 power-domains = <&pd_conn_enet1>;
 394                 status = "disabled";
 395         };
 396 };
 397
 398 &A53_0 {
 399         clocks = <&clk IMX8QM_A53_DIV>;
 400 };