1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include "fsl-imx8-ca53.dtsi"
8 #include <dt-bindings/clock/imx8qm-clock.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/soc/imx_rsrc.h>
11 #include <dt-bindings/soc/imx8_pd.h>
12 #include <dt-bindings/pinctrl/pads-imx8qm.h>
13 #include <dt-bindings/gpio/gpio.h>
16 compatible = "fsl,imx8qm";
17 interrupt-parent = <&gic>;
40 device_type = "memory";
41 reg = <0x00000000 0x80000000 0 0x40000000>;
42 /* DRAM space - 1, size : 1 GB DRAM */
45 gic: interrupt-controller@51a00000 {
46 compatible = "arm,gic-v3";
47 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
48 <0x0 0x51b00000 0 0xC0000>, /* GICR */
49 <0x0 0x52000000 0 0x2000>, /* GICC */
50 <0x0 0x52010000 0 0x1000>, /* GICH */
51 <0x0 0x52020000 0 0x20000>; /* GICV */
52 #interrupt-cells = <3>;
54 interrupts = <GIC_PPI 9
55 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
56 interrupt-parent = <&gic>;
60 compatible = "fsl,imx8-mu";
61 reg = <0x0 0x5d1c0000 0x0 0x10000>;
62 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
63 interrupt-parent = <&gic>;
64 fsl,scu_ap_mu_id = <0>;
68 compatible = "fsl,imx8qm-clk";
73 compatible = "fsl,imx8qm-iomuxc";
78 compatible = "simple-bus";
83 compatible = "nxp,imx8-pd";
85 #power-domain-cells = <0>;
89 pd_lsio_gpio0: PD_LSIO_GPIO_0 {
91 #power-domain-cells = <0>;
92 power-domains = <&pd_lsio>;
94 pd_lsio_gpio1: PD_LSIO_GPIO_1 {
96 #power-domain-cells = <0>;
97 power-domains = <&pd_lsio>;
99 pd_lsio_gpio2: PD_LSIO_GPIO_2 {
101 #power-domain-cells = <0>;
102 power-domains = <&pd_lsio>;
104 pd_lsio_gpio3: PD_LSIO_GPIO_3 {
106 #power-domain-cells = <0>;
107 power-domains = <&pd_lsio>;
109 pd_lsio_gpio4: PD_LSIO_GPIO_4 {
111 #power-domain-cells = <0>;
112 power-domains = <&pd_lsio>;
114 pd_lsio_gpio5: PD_LSIO_GPIO_5{
116 #power-domain-cells = <0>;
117 power-domains = <&pd_lsio>;
119 pd_lsio_gpio6:PD_LSIO_GPIO_6 {
121 #power-domain-cells = <0>;
122 power-domains = <&pd_lsio>;
124 pd_lsio_gpio7: PD_LSIO_GPIO_7 {
126 #power-domain-cells = <0>;
127 power-domains = <&pd_lsio>;
132 compatible = "nxp,imx8-pd";
134 #power-domain-cells = <0>;
135 #address-cells = <1>;
138 pd_conn_sdch0: PD_CONN_SDHC_0 {
140 #power-domain-cells = <0>;
141 power-domains = <&pd_conn>;
143 pd_conn_sdch1: PD_CONN_SDHC_1 {
145 #power-domain-cells = <0>;
146 power-domains = <&pd_conn>;
148 pd_conn_sdch2: PD_CONN_SDHC_2 {
150 #power-domain-cells = <0>;
151 power-domains = <&pd_conn>;
153 pd_conn_enet0: PD_CONN_ENET_0 {
155 #power-domain-cells = <0>;
156 power-domains = <&pd_conn>;
159 pd_conn_enet1: PD_CONN_ENET_1 {
161 #power-domain-cells = <0>;
162 power-domains = <&pd_conn>;
163 fsl,wakeup_irq = <262>;
168 compatible = "nxp,imx8-pd";
170 #power-domain-cells = <0>;
171 #address-cells = <1>;
174 pd_dma_lpi2c0: PD_DMA_I2C_0 {
176 #power-domain-cells = <0>;
177 power-domains = <&pd_dma>;
179 pd_dma_lpi2c1: PD_DMA_I2C_1 {
181 #power-domain-cells = <0>;
182 power-domains = <&pd_dma>;
184 pd_dma_lpi2c2:PD_DMA_I2C_2 {
186 #power-domain-cells = <0>;
187 power-domains = <&pd_dma>;
189 pd_dma_lpi2c3: PD_DMA_I2C_3 {
191 #power-domain-cells = <0>;
192 power-domains = <&pd_dma>;
194 pd_dma_lpi2c4: PD_DMA_I2C_4 {
196 #power-domain-cells = <0>;
197 power-domains = <&pd_dma>;
199 pd_dma_lpuart0: PD_DMA_UART0 {
201 #power-domain-cells = <0>;
202 power-domains = <&pd_dma>;
205 pd_dma_lpuart1: PD_DMA_UART1 {
207 #power-domain-cells = <0>;
208 power-domains = <&pd_dma>;
211 pd_dma_lpuart2: PD_DMA_UART2 {
213 #power-domain-cells = <0>;
214 power-domains = <&pd_dma>;
217 pd_dma_lpuart3: PD_DMA_UART3 {
219 #power-domain-cells = <0>;
220 power-domains = <&pd_dma>;
223 pd_dma_lpuart4: PD_DMA_UART4 {
225 #power-domain-cells = <0>;
226 power-domains = <&pd_dma>;
233 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
234 reg = <0x0 0x5a800000 0x0 0x4000>;
235 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
236 interrupt-parent = <&gic>;
237 clocks = <&clk IMX8QM_I2C0_CLK>,
238 <&clk IMX8QM_I2C0_IPG_CLK>;
239 clock-names = "per", "ipg";
240 assigned-clocks = <&clk IMX8QM_I2C0_CLK>;
241 assigned-clock-rates = <24000000>;
242 power-domains = <&pd_dma_lpi2c0>;
247 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
248 reg = <0x0 0x5a810000 0x0 0x4000>;
249 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
250 interrupt-parent = <&gic>;
251 clocks = <&clk IMX8QM_I2C1_CLK>,
252 <&clk IMX8QM_I2C1_IPG_CLK>;
253 clock-names = "per", "ipg";
254 assigned-clocks = <&clk IMX8QM_I2C1_CLK>;
255 assigned-clock-rates = <24000000>;
256 power-domains = <&pd_dma_lpi2c1>;
261 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
262 reg = <0x0 0x5a820000 0x0 0x4000>;
263 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
264 interrupt-parent = <&gic>;
265 clocks = <&clk IMX8QM_I2C2_CLK>,
266 <&clk IMX8QM_I2C2_IPG_CLK>;
267 clock-names = "per", "ipg";
268 assigned-clocks = <&clk IMX8QM_I2C2_CLK>;
269 assigned-clock-rates = <24000000>;
270 power-domains = <&pd_dma_lpi2c2>;
275 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
276 reg = <0x0 0x5a830000 0x0 0x4000>;
277 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
278 interrupt-parent = <&gic>;
279 clocks = <&clk IMX8QM_I2C3_CLK>,
280 <&clk IMX8QM_I2C3_IPG_CLK>;
281 clock-names = "per", "ipg";
282 assigned-clocks = <&clk IMX8QM_I2C3_CLK>;
283 assigned-clock-rates = <24000000>;
284 power-domains = <&pd_dma_lpi2c3>;
289 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
290 reg = <0x0 0x5a840000 0x0 0x4000>;
291 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
292 interrupt-parent = <&gic>;
293 clocks = <&clk IMX8QM_I2C4_CLK>,
294 <&clk IMX8QM_I2C4_IPG_CLK>;
295 clock-names = "per", "ipg";
296 assigned-clocks = <&clk IMX8QM_I2C4_CLK>;
297 assigned-clock-rates = <24000000>;
298 power-domains = <&pd_dma_lpi2c4>;
302 gpio0: gpio@5d080000 {
303 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
304 reg = <0x0 0x5d080000 0x0 0x10000>;
305 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
308 power-domains = <&pd_lsio_gpio0>;
309 interrupt-controller;
310 #interrupt-cells = <2>;
313 gpio1: gpio@5d090000 {
314 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
315 reg = <0x0 0x5d090000 0x0 0x10000>;
316 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
319 power-domains = <&pd_lsio_gpio1>;
320 interrupt-controller;
321 #interrupt-cells = <2>;
324 gpio2: gpio@5d0a0000 {
325 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
326 reg = <0x0 0x5d0a0000 0x0 0x10000>;
327 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
330 power-domains = <&pd_lsio_gpio2>;
331 interrupt-controller;
332 #interrupt-cells = <2>;
335 gpio3: gpio@5d0b0000 {
336 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
337 reg = <0x0 0x5d0b0000 0x0 0x10000>;
338 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
341 power-domains = <&pd_lsio_gpio3>;
342 interrupt-controller;
343 #interrupt-cells = <2>;
346 gpio4: gpio@5d0c0000 {
347 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
348 reg = <0x0 0x5d0c0000 0x0 0x10000>;
349 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
352 power-domains = <&pd_lsio_gpio4>;
353 interrupt-controller;
354 #interrupt-cells = <2>;
357 gpio5: gpio@5d0d0000 {
358 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
359 reg = <0x0 0x5d0d0000 0x0 0x10000>;
360 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
363 power-domains = <&pd_lsio_gpio5>;
364 interrupt-controller;
365 #interrupt-cells = <2>;
368 gpio6: gpio@5d0e0000 {
369 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
370 reg = <0x0 0x5d0e0000 0x0 0x10000>;
371 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
374 power-domains = <&pd_lsio_gpio6>;
375 interrupt-controller;
376 #interrupt-cells = <2>;
379 gpio7: gpio@5d0f0000 {
380 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
381 reg = <0x0 0x5d0f0000 0x0 0x10000>;
382 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
385 power-domains = <&pd_lsio_gpio7>;
386 interrupt-controller;
387 #interrupt-cells = <2>;
390 lpuart0: serial@5a060000 {
391 compatible = "fsl,imx8qm-lpuart";
392 reg = <0x0 0x5a060000 0x0 0x1000>;
393 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&clk IMX8QM_UART0_CLK>,
395 <&clk IMX8QM_UART0_IPG_CLK>;
396 clock-names = "per", "ipg";
397 assigned-clocks = <&clk IMX8QM_UART0_CLK>;
398 assigned-clock-rates = <80000000>;
399 power-domains = <&pd_dma_lpuart0>;
403 lpuart1: serial@5a070000 {
404 compatible = "fsl,imx8qm-lpuart";
405 reg = <0x0 0x5a070000 0x0 0x1000>;
406 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&clk IMX8QM_UART1_CLK>,
408 <&clk IMX8QM_UART1_IPG_CLK>;
409 clock-names = "per", "ipg";
410 assigned-clocks = <&clk IMX8QM_UART1_CLK>;
411 assigned-clock-rates = <80000000>;
412 power-domains = <&pd_dma_lpuart1>;
416 lpuart2: serial@5a080000 {
417 compatible = "fsl,imx8qm-lpuart";
418 reg = <0x0 0x5a080000 0x0 0x1000>;
419 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clk IMX8QM_UART2_CLK>,
421 <&clk IMX8QM_UART2_IPG_CLK>;
422 clock-names = "per", "ipg";
423 assigned-clocks = <&clk IMX8QM_UART2_CLK>;
424 assigned-clock-rates = <80000000>;
425 power-domains = <&pd_dma_lpuart2>;
429 lpuart3: serial@5a090000 {
430 compatible = "fsl,imx8qm-lpuart";
431 reg = <0x0 0x5a090000 0x0 0x1000>;
432 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&clk IMX8QM_UART3_CLK>,
434 <&clk IMX8QM_UART3_IPG_CLK>;
435 clock-names = "per", "ipg";
436 assigned-clocks = <&clk IMX8QM_UART3_CLK>;
437 assigned-clock-rates = <80000000>;
438 power-domains = <&pd_dma_lpuart3>;
442 lpuart4: serial@5a0a0000 {
443 compatible = "fsl,imx8qm-lpuart";
444 reg = <0x0 0x5a0a0000 0x0 0x1000>;
445 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&clk IMX8QM_UART4_CLK>,
447 <&clk IMX8QM_UART4_IPG_CLK>;
448 clock-names = "per", "ipg";
449 assigned-clocks = <&clk IMX8QM_UART4_CLK>;
450 assigned-clock-rates = <80000000>;
451 power-domains = <&pd_dma_lpuart4>;
455 usdhc1: usdhc@5b010000 {
456 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
457 interrupt-parent = <&gic>;
458 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
459 reg = <0x0 0x5b010000 0x0 0x10000>;
460 clocks = <&clk IMX8QM_SDHC0_IPG_CLK>,
461 <&clk IMX8QM_SDHC0_CLK>,
462 <&clk IMX8QM_CLK_DUMMY>;
463 clock-names = "ipg", "per", "ahb";
464 assigned-clocks = <&clk IMX8QM_SDHC0_DIV>;
465 assigned-clock-rates = <400000000>;
466 power-domains = <&pd_conn_sdch0>;
467 fsl,tuning-start-tap = <20>;
468 fsl,tuning-step= <2>;
472 usdhc2: usdhc@5b020000 {
473 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
474 interrupt-parent = <&gic>;
475 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
476 reg = <0x0 0x5b020000 0x0 0x10000>;
477 clocks = <&clk IMX8QM_SDHC1_IPG_CLK>,
478 <&clk IMX8QM_SDHC1_CLK>,
479 <&clk IMX8QM_CLK_DUMMY>;
480 clock-names = "ipg", "per", "ahb";
481 assigned-clocks = <&clk IMX8QM_SDHC1_DIV>;
482 assigned-clock-rates = <200000000>;
483 power-domains = <&pd_conn_sdch1>;
484 fsl,tuning-start-tap = <20>;
485 fsl,tuning-step= <2>;
489 usdhc3: usdhc@5b030000 {
490 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
491 interrupt-parent = <&gic>;
492 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
493 reg = <0x0 0x5b030000 0x0 0x10000>;
494 clocks = <&clk IMX8QM_SDHC2_IPG_CLK>,
495 <&clk IMX8QM_SDHC2_CLK>,
496 <&clk IMX8QM_CLK_DUMMY>;
497 clock-names = "ipg", "per", "ahb";
498 assigned-clocks = <&clk IMX8QM_SDHC2_DIV>;
499 assigned-clock-rates = <200000000>;
500 power-domains = <&pd_conn_sdch2>;
504 fec1: ethernet@5b040000 {
505 compatible = "fsl,imx8qm-fec", "fsl,imx7d-fec";
506 reg = <0x0 0x5b040000 0x0 0x10000>;
507 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&clk IMX8QM_ENET0_IPG_CLK>,
512 <&clk IMX8QM_ENET0_AHB_CLK>,
513 <&clk IMX8QM_ENET0_RGMII_TX_CLK>,
514 <&clk IMX8QM_ENET0_PTP_CLK>,
515 <&clk IMX8QM_ENET0_TX_CLK>;
516 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp",
518 assigned-clocks = <&clk IMX8QM_ENET0_ROOT_DIV>,
519 <&clk IMX8QM_ENET0_REF_DIV>;
520 assigned-clock-rates = <250000000>, <125000000>;
521 fsl,num-tx-queues=<3>;
522 fsl,num-rx-queues=<3>;
523 fsl,wakeup_irq = <0>;
524 power-domains = <&pd_conn_enet0>;
528 fec2: ethernet@5b050000 {
529 compatible = "fsl,imx8qm-fec", "fsl,imx7d-fec";
530 reg = <0x0 0x5b050000 0x0 0x10000>;
531 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&clk IMX8QM_ENET1_IPG_CLK>,
536 <&clk IMX8QM_ENET1_AHB_CLK>,
537 <&clk IMX8QM_ENET1_RGMII_TX_CLK>,
538 <&clk IMX8QM_ENET1_PTP_CLK>,
539 <&clk IMX8QM_ENET1_TX_CLK>;
540 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp",
542 assigned-clocks = <&clk IMX8QM_ENET1_ROOT_DIV>,
543 <&clk IMX8QM_ENET1_REF_DIV>;
544 assigned-clock-rates = <250000000>, <125000000>;
545 fsl,num-tx-queues=<3>;
546 fsl,num-rx-queues=<3>;
547 fsl,wakeup_irq = <0>;
548 power-domains = <&pd_conn_enet1>;
554 clocks = <&clk IMX8QM_A53_DIV>;