1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include "fsl-imx8-ca53.dtsi"
8 #include <dt-bindings/clock/imx8qm-clock.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/soc/imx_rsrc.h>
11 #include <dt-bindings/soc/imx8_pd.h>
12 #include <dt-bindings/pinctrl/pads-imx8qm.h>
13 #include <dt-bindings/gpio/gpio.h>
16 compatible = "fsl,imx8qm";
17 interrupt-parent = <&gic>;
47 device_type = "memory";
48 reg = <0x00000000 0x80000000 0 0x40000000>;
49 /* DRAM space - 1, size : 1 GB DRAM */
52 gic: interrupt-controller@51a00000 {
53 compatible = "arm,gic-v3";
54 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
55 <0x0 0x51b00000 0 0xC0000>, /* GICR */
56 <0x0 0x52000000 0 0x2000>, /* GICC */
57 <0x0 0x52010000 0 0x1000>, /* GICH */
58 <0x0 0x52020000 0 0x20000>; /* GICV */
59 #interrupt-cells = <3>;
61 interrupts = <GIC_PPI 9
62 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
63 interrupt-parent = <&gic>;
67 compatible = "fsl,imx8-mu";
68 reg = <0x0 0x5d1c0000 0x0 0x10000>;
69 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
70 interrupt-parent = <&gic>;
71 fsl,scu_ap_mu_id = <0>;
75 compatible = "fsl,imx8qm-clk";
80 compatible = "fsl,imx8qm-iomuxc";
85 compatible = "simple-bus";
90 compatible = "nxp,imx8-pd";
92 #power-domain-cells = <0>;
96 pd_lsio_gpio0: PD_LSIO_GPIO_0 {
98 #power-domain-cells = <0>;
99 power-domains = <&pd_lsio>;
101 pd_lsio_gpio1: PD_LSIO_GPIO_1 {
103 #power-domain-cells = <0>;
104 power-domains = <&pd_lsio>;
106 pd_lsio_gpio2: PD_LSIO_GPIO_2 {
108 #power-domain-cells = <0>;
109 power-domains = <&pd_lsio>;
111 pd_lsio_gpio3: PD_LSIO_GPIO_3 {
113 #power-domain-cells = <0>;
114 power-domains = <&pd_lsio>;
116 pd_lsio_gpio4: PD_LSIO_GPIO_4 {
118 #power-domain-cells = <0>;
119 power-domains = <&pd_lsio>;
121 pd_lsio_gpio5: PD_LSIO_GPIO_5{
123 #power-domain-cells = <0>;
124 power-domains = <&pd_lsio>;
126 pd_lsio_gpio6:PD_LSIO_GPIO_6 {
128 #power-domain-cells = <0>;
129 power-domains = <&pd_lsio>;
131 pd_lsio_gpio7: PD_LSIO_GPIO_7 {
133 #power-domain-cells = <0>;
134 power-domains = <&pd_lsio>;
139 compatible = "nxp,imx8-pd";
141 #power-domain-cells = <0>;
142 #address-cells = <1>;
145 pd_conn_sdch0: PD_CONN_SDHC_0 {
147 #power-domain-cells = <0>;
148 power-domains = <&pd_conn>;
150 pd_conn_sdch1: PD_CONN_SDHC_1 {
152 #power-domain-cells = <0>;
153 power-domains = <&pd_conn>;
155 pd_conn_sdch2: PD_CONN_SDHC_2 {
157 #power-domain-cells = <0>;
158 power-domains = <&pd_conn>;
160 pd_conn_enet0: PD_CONN_ENET_0 {
162 #power-domain-cells = <0>;
163 power-domains = <&pd_conn>;
166 pd_conn_enet1: PD_CONN_ENET_1 {
168 #power-domain-cells = <0>;
169 power-domains = <&pd_conn>;
170 fsl,wakeup_irq = <262>;
175 compatible = "nxp,imx8-pd";
177 #power-domain-cells = <0>;
178 #address-cells = <1>;
181 pd_dma_lpi2c0: PD_DMA_I2C_0 {
183 #power-domain-cells = <0>;
184 power-domains = <&pd_dma>;
186 pd_dma_lpi2c1: PD_DMA_I2C_1 {
188 #power-domain-cells = <0>;
189 power-domains = <&pd_dma>;
191 pd_dma_lpi2c2:PD_DMA_I2C_2 {
193 #power-domain-cells = <0>;
194 power-domains = <&pd_dma>;
196 pd_dma_lpi2c3: PD_DMA_I2C_3 {
198 #power-domain-cells = <0>;
199 power-domains = <&pd_dma>;
201 pd_dma_lpi2c4: PD_DMA_I2C_4 {
203 #power-domain-cells = <0>;
204 power-domains = <&pd_dma>;
206 pd_dma_lpuart0: PD_DMA_UART0 {
208 #power-domain-cells = <0>;
209 power-domains = <&pd_dma>;
212 pd_dma_lpuart1: PD_DMA_UART1 {
214 #power-domain-cells = <0>;
215 power-domains = <&pd_dma>;
218 pd_dma_lpuart2: PD_DMA_UART2 {
220 #power-domain-cells = <0>;
221 power-domains = <&pd_dma>;
224 pd_dma_lpuart3: PD_DMA_UART3 {
226 #power-domain-cells = <0>;
227 power-domains = <&pd_dma>;
230 pd_dma_lpuart4: PD_DMA_UART4 {
232 #power-domain-cells = <0>;
233 power-domains = <&pd_dma>;
240 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
241 reg = <0x0 0x5a800000 0x0 0x4000>;
242 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
243 interrupt-parent = <&gic>;
244 clocks = <&clk IMX8QM_I2C0_CLK>,
245 <&clk IMX8QM_I2C0_IPG_CLK>;
246 clock-names = "per", "ipg";
247 assigned-clocks = <&clk IMX8QM_I2C0_CLK>;
248 assigned-clock-rates = <24000000>;
249 power-domains = <&pd_dma_lpi2c0>;
254 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
255 reg = <0x0 0x5a810000 0x0 0x4000>;
256 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
257 interrupt-parent = <&gic>;
258 clocks = <&clk IMX8QM_I2C1_CLK>,
259 <&clk IMX8QM_I2C1_IPG_CLK>;
260 clock-names = "per", "ipg";
261 assigned-clocks = <&clk IMX8QM_I2C1_CLK>;
262 assigned-clock-rates = <24000000>;
263 power-domains = <&pd_dma_lpi2c1>;
268 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
269 reg = <0x0 0x5a820000 0x0 0x4000>;
270 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
271 interrupt-parent = <&gic>;
272 clocks = <&clk IMX8QM_I2C2_CLK>,
273 <&clk IMX8QM_I2C2_IPG_CLK>;
274 clock-names = "per", "ipg";
275 assigned-clocks = <&clk IMX8QM_I2C2_CLK>;
276 assigned-clock-rates = <24000000>;
277 power-domains = <&pd_dma_lpi2c2>;
282 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
283 reg = <0x0 0x5a830000 0x0 0x4000>;
284 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
285 interrupt-parent = <&gic>;
286 clocks = <&clk IMX8QM_I2C3_CLK>,
287 <&clk IMX8QM_I2C3_IPG_CLK>;
288 clock-names = "per", "ipg";
289 assigned-clocks = <&clk IMX8QM_I2C3_CLK>;
290 assigned-clock-rates = <24000000>;
291 power-domains = <&pd_dma_lpi2c3>;
296 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
297 reg = <0x0 0x5a840000 0x0 0x4000>;
298 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
299 interrupt-parent = <&gic>;
300 clocks = <&clk IMX8QM_I2C4_CLK>,
301 <&clk IMX8QM_I2C4_IPG_CLK>;
302 clock-names = "per", "ipg";
303 assigned-clocks = <&clk IMX8QM_I2C4_CLK>;
304 assigned-clock-rates = <24000000>;
305 power-domains = <&pd_dma_lpi2c4>;
309 gpio0: gpio@5d080000 {
310 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
311 reg = <0x0 0x5d080000 0x0 0x10000>;
312 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
315 power-domains = <&pd_lsio_gpio0>;
316 interrupt-controller;
317 #interrupt-cells = <2>;
320 gpio1: gpio@5d090000 {
321 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
322 reg = <0x0 0x5d090000 0x0 0x10000>;
323 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
326 power-domains = <&pd_lsio_gpio1>;
327 interrupt-controller;
328 #interrupt-cells = <2>;
331 gpio2: gpio@5d0a0000 {
332 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
333 reg = <0x0 0x5d0a0000 0x0 0x10000>;
334 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
337 power-domains = <&pd_lsio_gpio2>;
338 interrupt-controller;
339 #interrupt-cells = <2>;
342 gpio3: gpio@5d0b0000 {
343 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
344 reg = <0x0 0x5d0b0000 0x0 0x10000>;
345 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
348 power-domains = <&pd_lsio_gpio3>;
349 interrupt-controller;
350 #interrupt-cells = <2>;
353 gpio4: gpio@5d0c0000 {
354 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
355 reg = <0x0 0x5d0c0000 0x0 0x10000>;
356 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
359 power-domains = <&pd_lsio_gpio4>;
360 interrupt-controller;
361 #interrupt-cells = <2>;
364 gpio5: gpio@5d0d0000 {
365 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
366 reg = <0x0 0x5d0d0000 0x0 0x10000>;
367 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
370 power-domains = <&pd_lsio_gpio5>;
371 interrupt-controller;
372 #interrupt-cells = <2>;
375 gpio6: gpio@5d0e0000 {
376 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
377 reg = <0x0 0x5d0e0000 0x0 0x10000>;
378 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
381 power-domains = <&pd_lsio_gpio6>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
386 gpio7: gpio@5d0f0000 {
387 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
388 reg = <0x0 0x5d0f0000 0x0 0x10000>;
389 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
392 power-domains = <&pd_lsio_gpio7>;
393 interrupt-controller;
394 #interrupt-cells = <2>;
397 lpuart0: serial@5a060000 {
398 compatible = "fsl,imx8qm-lpuart";
399 reg = <0x0 0x5a060000 0x0 0x1000>;
400 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&clk IMX8QM_UART0_CLK>,
402 <&clk IMX8QM_UART0_IPG_CLK>;
403 clock-names = "per", "ipg";
404 assigned-clocks = <&clk IMX8QM_UART0_CLK>;
405 assigned-clock-rates = <80000000>;
406 power-domains = <&pd_dma_lpuart0>;
410 lpuart1: serial@5a070000 {
411 compatible = "fsl,imx8qm-lpuart";
412 reg = <0x0 0x5a070000 0x0 0x1000>;
413 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&clk IMX8QM_UART1_CLK>,
415 <&clk IMX8QM_UART1_IPG_CLK>;
416 clock-names = "per", "ipg";
417 assigned-clocks = <&clk IMX8QM_UART1_CLK>;
418 assigned-clock-rates = <80000000>;
419 power-domains = <&pd_dma_lpuart1>;
423 lpuart2: serial@5a080000 {
424 compatible = "fsl,imx8qm-lpuart";
425 reg = <0x0 0x5a080000 0x0 0x1000>;
426 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&clk IMX8QM_UART2_CLK>,
428 <&clk IMX8QM_UART2_IPG_CLK>;
429 clock-names = "per", "ipg";
430 assigned-clocks = <&clk IMX8QM_UART2_CLK>;
431 assigned-clock-rates = <80000000>;
432 power-domains = <&pd_dma_lpuart2>;
436 lpuart3: serial@5a090000 {
437 compatible = "fsl,imx8qm-lpuart";
438 reg = <0x0 0x5a090000 0x0 0x1000>;
439 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&clk IMX8QM_UART3_CLK>,
441 <&clk IMX8QM_UART3_IPG_CLK>;
442 clock-names = "per", "ipg";
443 assigned-clocks = <&clk IMX8QM_UART3_CLK>;
444 assigned-clock-rates = <80000000>;
445 power-domains = <&pd_dma_lpuart3>;
449 lpuart4: serial@5a0a0000 {
450 compatible = "fsl,imx8qm-lpuart";
451 reg = <0x0 0x5a0a0000 0x0 0x1000>;
452 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&clk IMX8QM_UART4_CLK>,
454 <&clk IMX8QM_UART4_IPG_CLK>;
455 clock-names = "per", "ipg";
456 assigned-clocks = <&clk IMX8QM_UART4_CLK>;
457 assigned-clock-rates = <80000000>;
458 power-domains = <&pd_dma_lpuart4>;
462 usdhc1: usdhc@5b010000 {
463 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
464 interrupt-parent = <&gic>;
465 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
466 reg = <0x0 0x5b010000 0x0 0x10000>;
467 clocks = <&clk IMX8QM_SDHC0_IPG_CLK>,
468 <&clk IMX8QM_SDHC0_CLK>,
469 <&clk IMX8QM_CLK_DUMMY>;
470 clock-names = "ipg", "per", "ahb";
471 assigned-clocks = <&clk IMX8QM_SDHC0_DIV>;
472 assigned-clock-rates = <400000000>;
473 power-domains = <&pd_conn_sdch0>;
474 fsl,tuning-start-tap = <20>;
475 fsl,tuning-step= <2>;
479 usdhc2: usdhc@5b020000 {
480 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
481 interrupt-parent = <&gic>;
482 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
483 reg = <0x0 0x5b020000 0x0 0x10000>;
484 clocks = <&clk IMX8QM_SDHC1_IPG_CLK>,
485 <&clk IMX8QM_SDHC1_CLK>,
486 <&clk IMX8QM_CLK_DUMMY>;
487 clock-names = "ipg", "per", "ahb";
488 assigned-clocks = <&clk IMX8QM_SDHC1_DIV>;
489 assigned-clock-rates = <200000000>;
490 power-domains = <&pd_conn_sdch1>;
491 fsl,tuning-start-tap = <20>;
492 fsl,tuning-step= <2>;
496 usdhc3: usdhc@5b030000 {
497 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
498 interrupt-parent = <&gic>;
499 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
500 reg = <0x0 0x5b030000 0x0 0x10000>;
501 clocks = <&clk IMX8QM_SDHC2_IPG_CLK>,
502 <&clk IMX8QM_SDHC2_CLK>,
503 <&clk IMX8QM_CLK_DUMMY>;
504 clock-names = "ipg", "per", "ahb";
505 assigned-clocks = <&clk IMX8QM_SDHC2_DIV>;
506 assigned-clock-rates = <200000000>;
507 power-domains = <&pd_conn_sdch2>;
511 fec1: ethernet@5b040000 {
512 compatible = "fsl,imx8qm-fec", "fsl,imx7d-fec";
513 reg = <0x0 0x5b040000 0x0 0x10000>;
514 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&clk IMX8QM_ENET0_IPG_CLK>,
519 <&clk IMX8QM_ENET0_AHB_CLK>,
520 <&clk IMX8QM_ENET0_RGMII_TX_CLK>,
521 <&clk IMX8QM_ENET0_PTP_CLK>,
522 <&clk IMX8QM_ENET0_TX_CLK>;
523 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp",
525 assigned-clocks = <&clk IMX8QM_ENET0_ROOT_DIV>,
526 <&clk IMX8QM_ENET0_REF_DIV>;
527 assigned-clock-rates = <250000000>, <125000000>;
528 fsl,num-tx-queues=<3>;
529 fsl,num-rx-queues=<3>;
530 fsl,wakeup_irq = <0>;
531 power-domains = <&pd_conn_enet0>;
535 fec2: ethernet@5b050000 {
536 compatible = "fsl,imx8qm-fec", "fsl,imx7d-fec";
537 reg = <0x0 0x5b050000 0x0 0x10000>;
538 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&clk IMX8QM_ENET1_IPG_CLK>,
543 <&clk IMX8QM_ENET1_AHB_CLK>,
544 <&clk IMX8QM_ENET1_RGMII_TX_CLK>,
545 <&clk IMX8QM_ENET1_PTP_CLK>,
546 <&clk IMX8QM_ENET1_TX_CLK>;
547 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp",
549 assigned-clocks = <&clk IMX8QM_ENET1_ROOT_DIV>,
550 <&clk IMX8QM_ENET1_REF_DIV>;
551 assigned-clock-rates = <250000000>, <125000000>;
552 fsl,num-tx-queues=<3>;
553 fsl,num-rx-queues=<3>;
554 fsl,wakeup_irq = <0>;
555 power-domains = <&pd_conn_enet1>;
561 clocks = <&clk IMX8QM_A53_DIV>;