arch/arm/dts/fsl-imx8qm-apalis.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * Copyright 2017-2019 Toradex
   4  */
   5
   6 /dts-v1/;
   7
   8 /* First 128KB is for PSCI ATF. */
   9 /memreserve/ 0x80000000 0x00020000;
  10
  11 #include "fsl-imx8qm.dtsi"
  12 #include "fsl-imx8qm-apalis-u-boot.dtsi"
  13
  14 / {
  15         model = "Toradex Apalis iMX8QM";
  16         compatible = "toradex,apalis-imx8qm", "fsl,imx8qm";
  17
  18         chosen {
  19                 bootargs = "console=ttyLP1,115200 earlycon=lpuart32,0x5a070000,115200";
  20                 stdout-path = &lpuart1;
  21         };
  22 };
  23
  24 &iomuxc {
  25         pinctrl-names = "default";
  26         pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>,
  27                     <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>,
  28                     <&pinctrl_gpio12>, <&pinctrl_gpio34>, <&pinctrl_gpio56>,
  29                     <&pinctrl_gpio7>, <&pinctrl_gpio8>, <&pinctrl_gpio_bkl_on>,
  30                     <&pinctrl_gpio_keys>, <&pinctrl_gpio_pwm0>,
  31                     <&pinctrl_gpio_pwm1>, <&pinctrl_gpio_pwm2>,
  32                     <&pinctrl_gpio_pwm3>, <&pinctrl_gpio_pwm_bkl>,
  33                     <&pinctrl_gpio_usbh_en>, <&pinctrl_gpio_usbh_oc_n>,
  34                     <&pinctrl_gpio_usbo1_en>, <&pinctrl_gpio_usbo1_oc_n>,
  35                     <&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>,
  36                     <&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>,
  37                     <&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>,
  38                     <&pinctrl_qspi1a_gpios>, <&pinctrl_sata1_act>,
  39                     <&pinctrl_sim0_gpios>, <&pinctrl_usdhc1_gpios>;
  40
  41         apalis-imx8qm {
  42                 pinctrl_gpio12: gpio12grp {
  43                         fsl,pins = <
  44                                 /* Apalis GPIO1 */
  45                                 SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08               0x06000021
  46                                 /* Apalis GPIO2 */
  47                                 SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09               0x06000021
  48                         >;
  49                 };
  50
  51                 pinctrl_gpio34: gpio34grp {
  52                         fsl,pins = <
  53                                 /* Apalis GPIO3 */
  54                                 SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12               0x06000021
  55                                 /* Apalis GPIO4 */
  56                                 SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13               0x06000021
  57                         >;
  58                 };
  59
  60                 pinctrl_gpio56: gpio56grp {
  61                         fsl,pins = <
  62                                 /* Apalis GPIO5 */
  63                                 SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01                0x06000021
  64                                 /* Apalis GPIO6 */
  65                                 SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02                0x06000021
  66                         >;
  67                 };
  68
  69                 pinctrl_gpio7: gpio7 {
  70                         fsl,pins = <
  71                                 /* Apalis GPIO7 */
  72                                 SC_P_MLB_SIG_LSIO_GPIO3_IO26                    0x00000021
  73                         >;
  74                 };
  75
  76                 pinctrl_gpio8: gpio8 {
  77                         fsl,pins = <
  78                                 /* Apalis GPIO8 */
  79                                 SC_P_MLB_DATA_LSIO_GPIO3_IO28                   0x00000021
  80                         >;
  81                 };
  82
  83                 pinctrl_gpio_keys: gpio-keys {
  84                         fsl,pins = <
  85                                 /* Apalis WAKE1_MICO */
  86                                 SC_P_SPI3_CS0_LSIO_GPIO2_IO20           0x06000021
  87                         >;
  88                 };
  89
  90                 pinctrl_fec1: fec1grp {
  91                         fsl,pins = <
  92                                 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD       0x000014a0 /* Use pads in 3.3V mode */
  93                                 SC_P_ENET0_MDC_CONN_ENET0_MDC                   0x06000020
  94                                 SC_P_ENET0_MDIO_CONN_ENET0_MDIO                 0x06000020
  95                                 SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
  96                                 SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC       0x06000020
  97                                 SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0     0x06000020
  98                                 SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1     0x06000020
  99                                 SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2     0x06000020
 100                                 SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3     0x06000020
 101                                 SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC       0x06000020
 102                                 SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
 103                                 SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0     0x06000020
 104                                 SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1     0x06000020
 105                                 SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2     0x06000020
 106                                 SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3     0x06000020
 107                                 SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M   0x06000020
 108                                 /* ETH_RESET# */
 109                                 SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11               0x06000020
 110                         >;
 111                 };
 112
 113                 pinctrl_gpio_bkl_on: gpio-bkl-on {
 114                         fsl,pins = <
 115                                 /* Apalis BKL_ON */
 116                                 SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04       0x00000021
 117                         >;
 118                 };
 119
 120                 /* Apalis I2C2 (DDC) */
 121                 pinctrl_lpi2c0: lpi2c0grp {
 122                         fsl,pins = <
 123                                 SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL       0x04000022
 124                                 SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA       0x04000022
 125                         >;
 126                 };
 127
 128                 pinctrl_cam1_gpios: cam1gpiosgrp {
 129                         fsl,pins = <
 130                                 /* Apalis CAM1_D7 */
 131                                 SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 0x00000021
 132                                 /* Apalis CAM1_D6 */
 133                                 SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 0x00000021
 134                                 /* Apalis CAM1_D5 */
 135                                 SC_P_ESAI0_TX0_LSIO_GPIO2_IO26          0x00000021
 136                                 /* Apalis CAM1_D4 */
 137                                 SC_P_ESAI0_TX1_LSIO_GPIO2_IO27          0x00000021
 138                                 /* Apalis CAM1_D3 */
 139                                 SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28      0x00000021
 140                                 /* Apalis CAM1_D2 */
 141                                 SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29      0x00000021
 142                                 /* Apalis CAM1_D1 */
 143                                 SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30      0x00000021
 144                                 /* Apalis CAM1_D0 */
 145                                 SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31      0x00000021
 146                                 /* Apalis CAM1_PCLK */
 147                                 SC_P_MCLK_IN0_LSIO_GPIO3_IO00           0x00000021
 148                                 /* Apalis CAM1_MCLK */
 149                                 SC_P_SPI3_SDO_LSIO_GPIO2_IO18           0x00000021
 150                                 /* Apalis CAM1_VSYNC */
 151                                 SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24         0x00000021
 152                                 /* Apalis CAM1_HSYNC */
 153                                 SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25         0x00000021
 154                         >;
 155                 };
 156
 157                 pinctrl_dap1_gpios: dap1gpiosgrp {
 158                         fsl,pins = <
 159                                 /* Apalis DAP1_MCLK */
 160                                 SC_P_SPI3_SDI_LSIO_GPIO2_IO19                   0x00000021
 161                                 /* Apalis DAP1_D_OUT */
 162                                 SC_P_SAI1_RXC_LSIO_GPIO3_IO12                   0x00000021
 163                                 /* Apalis DAP1_RESET */
 164                                 SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07                 0x00000021
 165                                 /* Apalis DAP1_BIT_CLK */
 166                                 SC_P_SPI0_CS1_LSIO_GPIO3_IO06                   0x00000021
 167                                 /* Apalis DAP1_D_IN */
 168                                 SC_P_SAI1_RXFS_LSIO_GPIO3_IO14                  0x00000021
 169                                 /* Apalis DAP1_SYNC */
 170                                 SC_P_SPI2_CS1_LSIO_GPIO3_IO11                   0x00000021
 171                                 /* Wi-Fi_I2S_EN# */
 172                                 SC_P_ESAI1_TX5_RX0_LSIO_GPIO2_IO13              0x00000021
 173                         >;
 174                 };
 175
 176                 pinctrl_esai0_gpios: esai0gpiosgrp {
 177                         fsl,pins = <
 178                                 /* Apalis LCD1_G1 */
 179                                 SC_P_ESAI0_FSR_LSIO_GPIO2_IO22                  0x00000021
 180                                 /* Apalis LCD1_G2 */
 181                                 SC_P_ESAI0_FST_LSIO_GPIO2_IO23                  0x00000021
 182                         >;
 183                 };
 184
 185                 pinctrl_fec2_gpios: fec2gpiosgrp {
 186                         fsl,pins = <
 187                                 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD       0x000014a0
 188                                 /* Apalis LCD1_R1 */
 189                                 SC_P_ENET1_MDC_LSIO_GPIO4_IO18                  0x00000021
 190                                 /* Apalis LCD1_R0 */
 191                                 SC_P_ENET1_MDIO_LSIO_GPIO4_IO17                 0x00000021
 192                                 /* Apalis LCD1_G0 */
 193                                 SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16      0x00000021
 194                                 /* Apalis LCD1_R7 */
 195                                 SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17         0x00000021
 196                                 /* Apalis LCD1_DE */
 197                                 SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18           0x00000021
 198                                 /* Apalis LCD1_HSYNC */
 199                                 SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19           0x00000021
 200                                 /* Apalis LCD1_VSYNC */
 201                                 SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20           0x00000021
 202                                 /* Apalis LCD1_PCLK */
 203                                 SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21           0x00000021
 204                                 /* Apalis LCD1_R6 */
 205                                 SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11         0x00000021
 206                                 /* Apalis LCD1_R5 */
 207                                 SC_P_ENET1_RGMII_TXC_LSIO_GPIO6_IO10            0x00000021
 208                                 /* Apalis LCD1_R4 */
 209                                 SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12           0x00000021
 210                                 /* Apalis LCD1_R3 */
 211                                 SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13           0x00000021
 212                                 /* Apalis LCD1_R2 */
 213                                 SC_P_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14           0x00000021
 214                         >;
 215                 };
 216
 217                 pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpio {
 218                         fsl,pins = <
 219                                 /* Apalis TS_2 */
 220                                 SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06             0x00000021
 221                         >;
 222                 };
 223
 224                 pinctrl_lvds1_i2c0_gpios: lvds1i2c0gpiosgrp {
 225                         fsl,pins = <
 226                                 /* Apalis LCD1_G6 */
 227                                 SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12             0x00000021
 228                                 /* Apalis LCD1_G7 */
 229                                 SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13             0x00000021
 230                         >;
 231                 };
 232
 233                 pinctrl_mipi_dsi1_gpios: mipidsi1gpiosgrp {
 234                         fsl,pins = <
 235                                 /* Apalis TS_4 */
 236                                 SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22         0x00000021
 237                         >;
 238                 };
 239
 240                 pinctrl_mlb_gpios: mlbgpiosgrp {
 241                         fsl,pins = <
 242                                 /* Apalis TS_1 */
 243                                 SC_P_MLB_CLK_LSIO_GPIO3_IO27                    0x00000021
 244                         >;
 245                 };
 246
 247                 pinctrl_qspi1a_gpios: qspi1agpiosgrp {
 248                         fsl,pins = <
 249                                 /* Apalis LCD1_B0 */
 250                                 SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26               0x00000021
 251                                 /* Apalis LCD1_B1 */
 252                                 SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25               0x00000021
 253                                 /* Apalis LCD1_B2 */
 254                                 SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24               0x00000021
 255                                 /* Apalis LCD1_B3 */
 256                                 SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23               0x00000021
 257                                 /* Apalis LCD1_B5 */
 258                                 SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22                 0x00000021
 259                                 /* Apalis LCD1_B7 */
 260                                 SC_P_QSPI1A_SCLK_LSIO_GPIO4_IO21                0x00000021
 261                                 /* Apalis LCD1_B4 */
 262                                 SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19               0x00000021
 263                                 /* Apalis LCD1_B6 */
 264                                 SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20               0x00000021
 265                         >;
 266                 };
 267
 268                 pinctrl_sim0_gpios: sim0gpiosgrp {
 269                         fsl,pins = <
 270                                 /* Apalis LCD1_G5 */
 271                                 SC_P_SIM0_CLK_LSIO_GPIO0_IO00                   0x00000021
 272                                 /* Apalis LCD1_G3 */
 273                                 SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05              0x00000021
 274                                 /* Apalis TS_5 */
 275                                 SC_P_SIM0_IO_LSIO_GPIO0_IO02                    0x00000021
 276                                 /* Apalis LCD1_G4 */
 277                                 SC_P_SIM0_RST_LSIO_GPIO0_IO01                   0x00000021
 278                         >;
 279                 };
 280
 281                 pinctrl_usdhc1_gpios: usdhc1gpiosgrp {
 282                         fsl,pins = <
 283                                 /* Apalis TS_6 */
 284                                 SC_P_USDHC1_STROBE_LSIO_GPIO5_IO23              0x00000021
 285                         >;
 286                 };
 287
 288                 pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en {
 289                         fsl,pins = <
 290                                 /* Apalis TS_3 */
 291                                 SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07             0x00000021
 292                         >;
 293                 };
 294
 295                 /* On-module I2C */
 296                 pinctrl_lpi2c1: lpi2c1grp {
 297                         fsl,pins = <
 298                                 SC_P_GPT0_CLK_DMA_I2C1_SCL              0x04000020
 299                                 SC_P_GPT0_CAPTURE_DMA_I2C1_SDA          0x04000020
 300                         >;
 301                 };
 302
 303                 /* Apalis I2C1 */
 304                 pinctrl_lpi2c2: lpi2c2grp {
 305                         fsl,pins = <
 306                                 SC_P_GPT1_CLK_DMA_I2C2_SCL              0x04000020
 307                                 SC_P_GPT1_CAPTURE_DMA_I2C2_SDA          0x04000020
 308                         >;
 309                 };
 310
 311                 /* Apalis I2C3 (CAM) */
 312                 pinctrl_lpi2c3: lpi2c3grp {
 313                         fsl,pins = <
 314                                 SC_P_SIM0_PD_DMA_I2C3_SCL               0x04000020
 315                                 SC_P_SIM0_POWER_EN_DMA_I2C3_SDA         0x04000020
 316                         >;
 317                 };
 318
 319                 /* Apalis UART3 */
 320                 pinctrl_lpuart0: lpuart0grp {
 321                         fsl,pins = <
 322                                 SC_P_UART0_RX_DMA_UART0_RX              0x06000020
 323                                 SC_P_UART0_TX_DMA_UART0_TX              0x06000020
 324                         >;
 325                 };
 326
 327                 /* Apalis UART1 */
 328                 pinctrl_lpuart1: lpuart1grp {
 329                         fsl,pins = <
 330                                 SC_P_UART1_RX_DMA_UART1_RX              0x06000020
 331                                 SC_P_UART1_TX_DMA_UART1_TX              0x06000020
 332                                 SC_P_UART1_CTS_B_DMA_UART1_CTS_B        0x06000020
 333                                 SC_P_UART1_RTS_B_DMA_UART1_RTS_B        0x06000020
 334                         >;
 335                 };
 336
 337                 pinctrl_lpuart1ctrl: lpuart1ctrlgrp {
 338                         fsl,pins = <
 339                                 /* Apalis UART1_DTR */
 340                                 SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06       0x00000021
 341                                 /* Apalis UART1_DSR */
 342                                 SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07       0x00000021
 343                                 /* Apalis UART1_DCD */
 344                                 SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10       0x00000021
 345                                 /* Apalis UART1_RI */
 346                                 SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11       0x00000021
 347                         >;
 348                 };
 349
 350                 /* Apalis UART4 */
 351                 pinctrl_lpuart2: lpuart2grp {
 352                         fsl,pins = <
 353                                 SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX        0x06000020
 354                                 SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX        0x06000020
 355                         >;
 356                 };
 357
 358                 /* Apalis UART2 */
 359                 pinctrl_lpuart3: lpuart3grp {
 360                         fsl,pins = <
 361                                 SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX        0x06000020
 362                                 SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX        0x06000020
 363                                 SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B   0x06000020
 364                                 SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B    0x06000020
 365                         >;
 366                 };
 367
 368                 /* Apalis PWM3 */
 369                 pinctrl_gpio_pwm0: gpiopwm0grp {
 370                         fsl,pins = <
 371                                 SC_P_UART0_RTS_B_LSIO_GPIO0_IO22        0x00000021
 372                         >;
 373                 };
 374
 375                 /* Apalis PWM4 */
 376                 pinctrl_gpio_pwm1: gpiopwm1grp {
 377                         fsl,pins = <
 378                                 SC_P_UART0_CTS_B_LSIO_GPIO0_IO23        0x00000021
 379                         >;
 380                 };
 381
 382                 /* Apalis PWM1 */
 383                 pinctrl_gpio_pwm2: gpiopwm2grp {
 384                         fsl,pins = <
 385                                 SC_P_GPT1_COMPARE_LSIO_GPIO0_IO19       0x00000021
 386                         >;
 387                 };
 388
 389                 /* Apalis PWM2 */
 390                 pinctrl_gpio_pwm3: gpiopwm3grp {
 391                         fsl,pins = <
 392                                 SC_P_GPT0_COMPARE_LSIO_GPIO0_IO16       0x00000021
 393                         >;
 394                 };
 395
 396                 /* Apalis BKL1_PWM */
 397                 pinctrl_gpio_pwm_bkl: gpiopwmbklgrp {
 398                         fsl,pins = <
 399                                 SC_P_LVDS1_GPIO00_LVDS1_GPIO0_IO00      0x00000021
 400                         >;
 401                 };
 402
 403                 /* Apalis USBH_EN */
 404                 pinctrl_gpio_usbh_en: gpiousbhen {
 405                         fsl,pins = <
 406                                 SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04        0x06000060
 407                         >;
 408                 };
 409
 410                 /* Apalis USBH_OC# */
 411                 pinctrl_gpio_usbh_oc_n: gpiousbhocn {
 412                         fsl,pins = <
 413                                 SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06        0x06000060
 414                         >;
 415                 };
 416
 417                 /* Apalis USBO1_EN */
 418                 pinctrl_gpio_usbo1_en: gpiousbo1en {
 419                         fsl,pins = <
 420                                 SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03        0x06000060
 421                         >;
 422                 };
 423
 424                 /* Apalis USBO1_OC# */
 425                 pinctrl_gpio_usbo1_oc_n: gpiousbo1ocn {
 426                         fsl,pins = <
 427                                 SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05        0x06000060
 428                         >;
 429                 };
 430
 431                 pinctrl_usdhc1: usdhc1grp {
 432                         fsl,pins = <
 433                                 SC_P_EMMC0_CLK_CONN_EMMC0_CLK           0x06000041
 434                                 SC_P_EMMC0_CMD_CONN_EMMC0_CMD           0x00000021
 435                                 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0       0x00000021
 436                                 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1       0x00000021
 437                                 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2       0x00000021
 438                                 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3       0x00000021
 439                                 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4       0x00000021
 440                                 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000021
 441                                 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000021
 442                                 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000021
 443                                 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x06000041
 444                                 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B   0x00000021
 445                         >;
 446                 };
 447
 448                 pinctrl_sata1_act: sata1actgrp {
 449                         fsl,pins = <
 450                                 /* Apalis SATA1_ACT# */
 451                                 SC_P_ESAI1_TX0_LSIO_GPIO2_IO08          0x00000021
 452                         >;
 453                 };
 454
 455                 pinctrl_mmc1_cd: mmc1cdgrp {
 456                         fsl,pins = <
 457                                 /* Apalis MMC1_CD# */
 458                                 SC_P_ESAI1_TX1_LSIO_GPIO2_IO09          0x00000021
 459                         >;
 460                 };
 461
 462                 pinctrl_usdhc2: usdhc2grp {
 463                         fsl,pins = <
 464                                 SC_P_USDHC1_CLK_CONN_USDHC1_CLK         0x06000041
 465                                 SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x00000021
 466                                 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x00000021
 467                                 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x00000021
 468                                 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x00000021
 469                                 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x00000021
 470                                 SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4     0x00000021
 471                                 SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5     0x00000021
 472                                 SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6     0x00000021
 473                                 SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7     0x00000021
 474                                 /* On-module PMIC use */
 475                                 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
 476                         >;
 477                 };
 478
 479                 pinctrl_sd1_cd: sd1cdgrp {
 480                         fsl,pins = <
 481                                 /* Apalis SD1_CD# */
 482                                 SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12        0x00000021
 483                         >;
 484                 };
 485
 486                 pinctrl_usdhc3: usdhc3grp {
 487                         fsl,pins = <
 488                                 SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000041
 489                                 SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000021
 490                                 SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000021
 491                                 SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000021
 492                                 SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2     0x00000021
 493                                 SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3     0x00000021
 494                                 /* On-module PMIC use */
 495                                 SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021
 496                         >;
 497                 };
 498         };
 499 };
 500
 501 &fec1 {
 502         pinctrl-names = "default";
 503         pinctrl-0 = <&pinctrl_fec1>;
 504         fsl,magic-packet;
 505         phy-handle = <&ethphy0>;
 506         phy-mode = "rgmii";
 507         phy-reset-duration = <10>;
 508         phy-reset-gpios = <&gpio1 11 1>;
 509         status = "okay";
 510
 511         mdio {
 512                 #address-cells = <1>;
 513                 #size-cells = <0>;
 514
 515                 ethphy0: ethernet-phy@7 {
 516                         compatible = "ethernet-phy-ieee802.3-c22";
 517                         reg = <7>;
 518                 };
 519         };
 520 };
 521
 522 /* Apalis I2C2 (DDC) */
 523 &i2c0 {
 524         #address-cells = <1>;
 525         #size-cells = <0>;
 526         pinctrl-names = "default";
 527         pinctrl-0 = <&pinctrl_lpi2c0>;
 528         clock-frequency = <100000>;
 529         status = "okay";
 530 };
 531
 532 /* On-module I2C */
 533 &i2c1 {
 534         #address-cells = <1>;
 535         #size-cells = <0>;
 536         clock-frequency = <100000>;
 537         pinctrl-names = "default";
 538         pinctrl-0 = <&pinctrl_lpi2c1>;
 539         status = "okay";
 540 };
 541
 542 /* Apalis I2C1 */
 543 &i2c2 {
 544         #address-cells = <1>;
 545         #size-cells = <0>;
 546         clock-frequency = <100000>;
 547         pinctrl-names = "default";
 548         pinctrl-0 = <&pinctrl_lpi2c2>;
 549         status = "okay";
 550 };
 551
 552 /* Apalis I2C3 (CAM) */
 553 &i2c3 {
 554         #address-cells = <1>;
 555         #size-cells = <0>;
 556         clock-frequency = <100000>;
 557         pinctrl-names = "default";
 558         pinctrl-0 = <&pinctrl_lpi2c3>;
 559         status = "okay";
 560 };
 561
 562 /* Apalis UART3 */
 563 &lpuart0 {
 564         pinctrl-names = "default";
 565         pinctrl-0 = <&pinctrl_lpuart0>;
 566         status = "okay";
 567 };
 568
 569 /* Apalis UART1 */
 570 &lpuart1 {
 571         pinctrl-names = "default";
 572         pinctrl-0 = <&pinctrl_lpuart1>;
 573         status = "okay";
 574 };
 575
 576 /* Apalis UART4 */
 577 &lpuart2 {
 578         pinctrl-names = "default";
 579         pinctrl-0 = <&pinctrl_lpuart2>;
 580         status = "okay";
 581 };
 582
 583 /* Apalis UART2 */
 584 &lpuart3 {
 585         pinctrl-names = "default";
 586         pinctrl-0 = <&pinctrl_lpuart3>;
 587         status = "okay";
 588 };
 589
 590 /* eMMC */
 591 &usdhc1 {
 592         pinctrl-names = "default";
 593         pinctrl-0 = <&pinctrl_usdhc1>;
 594         bus-width = <8>;
 595         non-removable;
 596         status = "okay";
 597 };
 598
 599 /* Apalis MMC1 */
 600 &usdhc2 {
 601         pinctrl-names = "default";
 602         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>;
 603         bus-width = <8>;
 604         cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */
 605         status = "okay";
 606 };
 607
 608 /* Apalis SD1 */
 609 &usdhc3 {
 610         pinctrl-names = "default";
 611         pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>;
 612         bus-width = <4>;
 613         cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */
 614         status = "okay";
 615 };