arch/arm/dts/fsl-imx8dx.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include "fsl-imx8-ca35.dtsi"
   8 #include <dt-bindings/soc/imx_rsrc.h>
   9 #include <dt-bindings/soc/imx8_pd.h>
  10 #include <dt-bindings/clock/imx8qxp-clock.h>
  11 #include <dt-bindings/input/input.h>
  12 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/thermal/thermal.h>
  15
  16 / {
  17         model = "Freescale i.MX8DX";
  18         compatible = "fsl,imx8dx", "fsl,imx8qxp";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 ethernet0 = &fec1;
  25                 ethernet1 = &fec2;
  26                 serial0 = &lpuart0;
  27                 mmc0 = &usdhc1;
  28                 mmc1 = &usdhc2;
  29                 mmc2 = &usdhc3;
  30                 i2c0 = &i2c0;
  31                 i2c1 = &i2c1;
  32                 i2c2 = &i2c2;
  33                 i2c3 = &i2c3;
  34                 gpio0 = &gpio0;
  35                 gpio1 = &gpio1;
  36                 gpio2 = &gpio2;
  37                 gpio3 = &gpio3;
  38                 gpio4 = &gpio4;
  39                 gpio5 = &gpio5;
  40                 gpio6 = &gpio6;
  41                 gpio7 = &gpio7;
  42         };
  43
  44         memory@80000000 {
  45                 device_type = "memory";
  46                 reg = <0x00000000 0x80000000 0 0x40000000>;
  47                       /* DRAM space - 1, size : 1 GB DRAM */
  48         };
  49
  50         reserved-memory {
  51                 #address-cells = <2>;
  52                 #size-cells = <2>;
  53                 ranges;
  54
  55                 /*
  56                  * reserved-memory layout
  57                  * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
  58                  * Shouldn't be used at A core and Linux side.
  59                  *
  60                  */
  61                 decoder_boot: decoder_boot@0x84000000 {
  62                         no-map;
  63                         reg = <0 0x84000000 0 0x2000000>;
  64                 };
  65                 encoder_boot: encoder_boot@0x86000000 {
  66                         no-map;
  67                         reg = <0 0x86000000 0 0x2000000>;
  68                 };
  69                 rpmsg_reserved: rpmsg@0x90000000 {
  70                         no-map;
  71                         reg = <0 0x90000000 0 0x400000>;
  72                 };
  73                 decoder_rpc: decoder_rpc@0x90400000 {
  74                         no-map;
  75                         reg = <0 0x90400000 0 0x1000000>;
  76                 };
  77                 encoder_rpc: encoder_rpc@0x91400000 {
  78                         no-map;
  79                         reg = <0 0x91400000 0 0x1000000>;
  80                 };
  81                 dsp_reserved: dsp@0x92400000 {
  82                         no-map;
  83                         reg = <0 0x92400000 0 0x2000000>;
  84                 };
  85                 decoder_str: str@0x94400000 {
  86                         no-map;
  87                         reg = <0 0x94400000 0 0x1800000>;
  88                 };
  89                 /* global autoconfigured region for contiguous allocations */
  90                 linux,cma {
  91                         compatible = "shared-dma-pool";
  92                         reusable;
  93                         size = <0 0x28000000>;
  94                         alloc-ranges = <0 0x96000000 0 0x28000000>;
  95                         linux,cma-default;
  96                 };
  97         };
  98
  99         gic: interrupt-controller@51a00000 {
 100                 compatible = "arm,gic-v3";
 101                 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
 102                       <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
 103                 #interrupt-cells = <3>;
 104                 interrupt-controller;
 105                 interrupts = <GIC_PPI 9
 106                         (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
 107                 interrupt-parent = <&gic>;
 108         };
 109
 110         mu: mu@5d1c0000 {
 111                 compatible = "fsl,imx8-mu";
 112                 reg = <0x0 0x5d1c0000 0x0 0x10000>;
 113                 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 114                 interrupt-parent = <&gic>;
 115                 status = "okay";
 116
 117                 clk: clk {
 118                         compatible = "fsl,imx8qxp-clk";
 119                         #clock-cells = <1>;
 120                 };
 121
 122                 iomuxc: iomuxc {
 123                         compatible = "fsl,imx8qxp-iomuxc";
 124                 };
 125         };
 126
 127         imx8qx-pm {
 128                 compatible = "simple-bus";
 129                 #address-cells = <1>;
 130                 #size-cells = <0>;
 131
 132                 pd_lsio: PD_LSIO {
 133                         compatible = "nxp,imx8-pd";
 134                         reg = <SC_R_LAST>;
 135                         #power-domain-cells = <0>;
 136                         #address-cells = <1>;
 137                         #size-cells = <0>;
 138
 139                         pd_lsio_gpio0: PD_LSIO_GPIO_0 {
 140                                 reg = <SC_R_GPIO_0>;
 141                                 #power-domain-cells = <0>;
 142                                 power-domains = <&pd_lsio>;
 143                         };
 144                         pd_lsio_gpio1: PD_LSIO_GPIO_1 {
 145                                 reg = <SC_R_GPIO_1>;
 146                                 #power-domain-cells = <0>;
 147                                 power-domains = <&pd_lsio>;
 148                         };
 149                         pd_lsio_gpio2: PD_LSIO_GPIO_2 {
 150                                 reg = <SC_R_GPIO_2>;
 151                                 #power-domain-cells = <0>;
 152                                 power-domains = <&pd_lsio>;
 153                         };
 154                         pd_lsio_gpio3: PD_LSIO_GPIO_3 {
 155                                 reg = <SC_R_GPIO_3>;
 156                                 #power-domain-cells = <0>;
 157                                 power-domains = <&pd_lsio>;
 158                         };
 159                         pd_lsio_gpio4: PD_LSIO_GPIO_4 {
 160                                 reg = <SC_R_GPIO_4>;
 161                                 #power-domain-cells = <0>;
 162                                 power-domains = <&pd_lsio>;
 163                         };
 164                         pd_lsio_gpio5: PD_LSIO_GPIO_5{
 165                                 reg = <SC_R_GPIO_5>;
 166                                 #power-domain-cells = <0>;
 167                                 power-domains = <&pd_lsio>;
 168                         };
 169                         pd_lsio_gpio6: PD_LSIO_GPIO_6 {
 170                                 reg = <SC_R_GPIO_6>;
 171                                 #power-domain-cells = <0>;
 172                                 power-domains = <&pd_lsio>;
 173                         };
 174                         pd_lsio_gpio7: PD_LSIO_GPIO_7 {
 175                                 reg = <SC_R_GPIO_7>;
 176                                 #power-domain-cells = <0>;
 177                                 power-domains = <&pd_lsio>;
 178                         };
 179                 };
 180
 181                 pd_conn: PD_CONN {
 182                         compatible = "nxp,imx8-pd";
 183                         reg = <SC_R_LAST>;
 184                         #power-domain-cells = <0>;
 185                         #address-cells = <1>;
 186                         #size-cells = <0>;
 187
 188                         pd_conn_sdch0: PD_CONN_SDHC_0 {
 189                                 reg = <SC_R_SDHC_0>;
 190                                 #power-domain-cells = <0>;
 191                                 power-domains = <&pd_conn>;
 192                         };
 193                         pd_conn_sdch1: PD_CONN_SDHC_1 {
 194                                 reg = <SC_R_SDHC_1>;
 195                                 #power-domain-cells = <0>;
 196                                 power-domains = <&pd_conn>;
 197                         };
 198                         pd_conn_sdch2: PD_CONN_SDHC_2 {
 199                                 reg = <SC_R_SDHC_2>;
 200                                 #power-domain-cells = <0>;
 201                                 power-domains = <&pd_conn>;
 202                         };
 203                         pd_conn_enet0: PD_CONN_ENET_0 {
 204                                 reg = <SC_R_ENET_0>;
 205                                 #power-domain-cells = <0>;
 206                                 power-domains = <&pd_conn>;
 207                         };
 208                         pd_conn_enet1: PD_CONN_ENET_1 {
 209                                 reg = <SC_R_ENET_1>;
 210                                 #power-domain-cells = <0>;
 211                                 power-domains = <&pd_conn>;
 212                         };
 213                 };
 214
 215                 pd_dma: PD_DMA {
 216                         compatible = "nxp,imx8-pd";
 217                         reg = <SC_R_LAST>;
 218                         #power-domain-cells = <0>;
 219                         #address-cells = <1>;
 220                         #size-cells = <0>;
 221
 222                         pd_dma_lpi2c0: PD_DMA_I2C_0 {
 223                                 reg = <SC_R_I2C_0>;
 224                                 #power-domain-cells = <0>;
 225                                 power-domains = <&pd_dma>;
 226                         };
 227                         pd_dma_lpi2c1: PD_DMA_I2C_1 {
 228                                 reg = <SC_R_I2C_1>;
 229                                 #power-domain-cells = <0>;
 230                                 power-domains = <&pd_dma>;
 231                         };
 232                         pd_dma_lpi2c2:PD_DMA_I2C_2 {
 233                                 reg = <SC_R_I2C_2>;
 234                                 #power-domain-cells = <0>;
 235                                 power-domains = <&pd_dma>;
 236                         };
 237                         pd_dma_lpi2c3: PD_DMA_I2C_3 {
 238                                 reg = <SC_R_I2C_3>;
 239                                 #power-domain-cells = <0>;
 240                                 power-domains = <&pd_dma>;
 241                         };
 242                         pd_dma_lpuart0: PD_DMA_UART0 {
 243                                 reg = <SC_R_UART_0>;
 244                                 #power-domain-cells = <0>;
 245                                 power-domains = <&pd_dma>;
 246                                 wakeup-irq = <225>;
 247                         };
 248                         pd_dma_lpuart1: PD_DMA_UART1 {
 249                                 reg = <SC_R_UART_1>;
 250                                 #power-domain-cells = <0>;
 251                                 power-domains = <&pd_dma>;
 252                         };
 253                         pd_dma_lpuart2: PD_DMA_UART2 {
 254                                 reg = <SC_R_UART_2>;
 255                                 #power-domain-cells = <0>;
 256                                 power-domains = <&pd_dma>;
 257                         };
 258                         pd_dma_lpuart3: PD_DMA_UART3 {
 259                                 reg = <SC_R_UART_3>;
 260                                 #power-domain-cells = <0>;
 261                                 power-domains = <&pd_dma>;
 262                         };
 263                 };
 264         };
 265
 266         i2c0: i2c@5a800000 {
 267                 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
 268                 reg = <0x0 0x5a800000 0x0 0x4000>;
 269                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 270                 interrupt-parent = <&gic>;
 271                 clocks = <&clk IMX8QXP_I2C0_CLK>;
 272                 clock-names = "per";
 273                 assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
 274                 assigned-clock-rates = <24000000>;
 275                 power-domains = <&pd_dma_lpi2c0>;
 276                 #address-cells = <1>;
 277                 #size-cells = <0>;
 278                 status = "disabled";
 279         };
 280
 281         i2c1: i2c@5a810000 {
 282                 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
 283                 reg = <0x0 0x5a810000 0x0 0x4000>;
 284                 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 285                 interrupt-parent = <&gic>;
 286                 clocks = <&clk IMX8QXP_I2C1_CLK>,
 287                         <&clk IMX8QXP_I2C1_IPG_CLK>;
 288                 clock-names = "per", "ipg";
 289                 assigned-clocks = <&clk IMX8QXP_I2C1_CLK>;
 290                 assigned-clock-rates = <24000000>;
 291                 power-domains = <&pd_dma_lpi2c1>;
 292                 #address-cells = <1>;
 293                 #size-cells = <0>;
 294                 status = "disabled";
 295         };
 296
 297         i2c2: i2c@5a820000 {
 298                 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
 299                 reg = <0x0 0x5a820000 0x0 0x4000>;
 300                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
 301                 interrupt-parent = <&gic>;
 302                 clocks = <&clk IMX8QXP_I2C2_CLK>;
 303                 clock-names = "per";
 304                 assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
 305                 assigned-clock-rates = <24000000>;
 306                 power-domains = <&pd_dma_lpi2c2>;
 307                 #address-cells = <1>;
 308                 #size-cells = <0>;
 309                 status = "disabled";
 310         };
 311
 312         i2c3: i2c@5a830000 {
 313                 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
 314                 reg = <0x0 0x5a830000 0x0 0x4000>;
 315                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 316                 interrupt-parent = <&gic>;
 317                 clocks = <&clk IMX8QXP_I2C3_CLK>,
 318                         <&clk IMX8QXP_I2C3_IPG_CLK>;
 319                 clock-names = "per", "ipg";
 320                 assigned-clocks = <&clk IMX8QXP_I2C3_CLK>;
 321                 assigned-clock-rates = <24000000>;
 322                 power-domains = <&pd_dma_lpi2c3>;
 323                 #address-cells = <1>;
 324                 #size-cells = <0>;
 325                 status = "disabled";
 326         };
 327
 328         gpio0: gpio@5d080000 {
 329                 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
 330                 reg = <0x0 0x5d080000 0x0 0x10000>;
 331                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 332                 gpio-controller;
 333                 #gpio-cells = <2>;
 334                 power-domains = <&pd_lsio_gpio0>;
 335                 interrupt-controller;
 336                 #interrupt-cells = <2>;
 337         };
 338
 339         gpio1: gpio@5d090000 {
 340                 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
 341                 reg = <0x0 0x5d090000 0x0 0x10000>;
 342                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 343                 gpio-controller;
 344                 #gpio-cells = <2>;
 345                 power-domains = <&pd_lsio_gpio1>;
 346                 interrupt-controller;
 347                 #interrupt-cells = <2>;
 348         };
 349
 350         gpio2: gpio@5d0a0000 {
 351                 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
 352                 reg = <0x0 0x5d0a0000 0x0 0x10000>;
 353                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 354                 gpio-controller;
 355                 #gpio-cells = <2>;
 356                 power-domains = <&pd_lsio_gpio2>;
 357                 interrupt-controller;
 358                 #interrupt-cells = <2>;
 359         };
 360
 361         gpio3: gpio@5d0b0000 {
 362                 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
 363                 reg = <0x0 0x5d0b0000 0x0 0x10000>;
 364                 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 365                 gpio-controller;
 366                 #gpio-cells = <2>;
 367                 power-domains = <&pd_lsio_gpio3>;
 368                 interrupt-controller;
 369                 #interrupt-cells = <2>;
 370         };
 371
 372         gpio4: gpio@5d0c0000 {
 373                 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
 374                 reg = <0x0 0x5d0c0000 0x0 0x10000>;
 375                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 376                 gpio-controller;
 377                 #gpio-cells = <2>;
 378                 power-domains = <&pd_lsio_gpio4>;
 379                 interrupt-controller;
 380                 #interrupt-cells = <2>;
 381         };
 382
 383         gpio5: gpio@5d0d0000 {
 384                 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
 385                 reg = <0x0 0x5d0d0000 0x0 0x10000>;
 386                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 387                 gpio-controller;
 388                 #gpio-cells = <2>;
 389                 power-domains = <&pd_lsio_gpio5>;
 390                 interrupt-controller;
 391                 #interrupt-cells = <2>;
 392         };
 393
 394         gpio6: gpio@5d0e0000 {
 395                 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
 396                 reg = <0x0 0x5d0e0000 0x0 0x10000>;
 397                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 398                 gpio-controller;
 399                 #gpio-cells = <2>;
 400                 power-domains = <&pd_lsio_gpio6>;
 401                 interrupt-controller;
 402                 #interrupt-cells = <2>;
 403         };
 404
 405         gpio7: gpio@5d0f0000 {
 406                 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
 407                 reg = <0x0 0x5d0f0000 0x0 0x10000>;
 408                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 409                 gpio-controller;
 410                 #gpio-cells = <2>;
 411                 power-domains = <&pd_lsio_gpio7>;
 412                 interrupt-controller;
 413                 #interrupt-cells = <2>;
 414         };
 415
 416         lpuart0: serial@5a060000 {
 417                 compatible = "fsl,imx8qm-lpuart";
 418                 reg = <0x0 0x5a060000 0x0 0x1000>;
 419                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 420                 clocks = <&clk IMX8QXP_UART0_CLK>,
 421                          <&clk IMX8QXP_UART0_IPG_CLK>;
 422                 clock-names = "per", "ipg";
 423                 assigned-clocks = <&clk IMX8QXP_UART0_CLK>;
 424                 assigned-clock-rates = <80000000>;
 425                 power-domains = <&pd_dma_lpuart0>;
 426                 status = "disabled";
 427         };
 428
 429         lpuart1: serial@5a070000 {
 430                 compatible = "fsl,imx8qm-lpuart";
 431                 reg = <0x0 0x5a070000 0x0 0x1000>;
 432                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 433                 clocks = <&clk IMX8QXP_UART1_CLK>,
 434                          <&clk IMX8QXP_UART1_IPG_CLK>;
 435                 clock-names = "per", "ipg";
 436                 assigned-clocks = <&clk IMX8QXP_UART1_CLK>;
 437                 assigned-clock-rates = <80000000>;
 438                 power-domains = <&pd_dma_lpuart1>;
 439                 status = "disabled";
 440         };
 441
 442         lpuart2: serial@5a080000 {
 443                 compatible = "fsl,imx8qm-lpuart";
 444                 reg = <0x0 0x5a080000 0x0 0x1000>;
 445                 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
 446                 clocks = <&clk IMX8QXP_UART2_CLK>,
 447                          <&clk IMX8QXP_UART2_IPG_CLK>;
 448                 clock-names = "per", "ipg";
 449                 assigned-clocks = <&clk IMX8QXP_UART2_CLK>;
 450                 assigned-clock-rates = <80000000>;
 451                 power-domains = <&pd_dma_lpuart2>;
 452                 status = "disabled";
 453         };
 454
 455         lpuart3: serial@5a090000 {
 456                 compatible = "fsl,imx8qm-lpuart";
 457                 reg = <0x0 0x5a090000 0x0 0x1000>;
 458                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
 459                 clocks = <&clk IMX8QXP_UART3_CLK>,
 460                          <&clk IMX8QXP_UART3_IPG_CLK>;
 461                 clock-names = "per", "ipg";
 462                 assigned-clocks = <&clk IMX8QXP_UART3_CLK>;
 463                 assigned-clock-rates = <80000000>;
 464                 power-domains = <&pd_dma_lpuart3>;
 465                 status = "disabled";
 466         };
 467
 468         usdhc1: usdhc@5b010000 {
 469                 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
 470                 interrupt-parent = <&gic>;
 471                 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
 472                 reg = <0x0 0x5b010000 0x0 0x10000>;
 473                 clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>,
 474                         <&clk IMX8QXP_SDHC0_CLK>,
 475                         <&clk IMX8QXP_CLK_DUMMY>;
 476                 clock-names = "ipg", "per", "ahb";
 477                 assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>;
 478                 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
 479                 assigned-clock-rates = <0>, <400000000>;
 480                 power-domains = <&pd_conn_sdch0>;
 481                 fsl,tuning-start-tap = <20>;
 482                 fsl,tuning-step= <2>;
 483                 status = "disabled";
 484         };
 485
 486         usdhc2: usdhc@5b020000 {
 487                 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
 488                 interrupt-parent = <&gic>;
 489                 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
 490                 reg = <0x0 0x5b020000 0x0 0x10000>;
 491                 clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>,
 492                         <&clk IMX8QXP_SDHC1_CLK>,
 493                         <&clk IMX8QXP_CLK_DUMMY>;
 494                 clock-names = "ipg", "per", "ahb";
 495                 assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>;
 496                 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
 497                 assigned-clock-rates = <0>, <200000000>;
 498                 power-domains = <&pd_conn_sdch1>;
 499                 fsl,tuning-start-tap = <20>;
 500                 fsl,tuning-step= <2>;
 501                 status = "disabled";
 502         };
 503
 504         usdhc3: usdhc@5b030000 {
 505                 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
 506                 interrupt-parent = <&gic>;
 507                 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
 508                 reg = <0x0 0x5b030000 0x0 0x10000>;
 509                 clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>,
 510                         <&clk IMX8QXP_SDHC2_CLK>,
 511                         <&clk IMX8QXP_CLK_DUMMY>;
 512                 clock-names = "ipg", "per", "ahb";
 513                 assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>;
 514                 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
 515                 assigned-clock-rates = <0>, <200000000>;
 516                 power-domains = <&pd_conn_sdch2>;
 517                 status = "disabled";
 518         };
 519
 520         fec1: ethernet@5b040000 {
 521                 compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
 522                 reg = <0x0 0x5b040000 0x0 0x10000>;
 523                 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 524                                 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 525                                 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 526                                 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
 527                 clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>,
 528                         <&clk IMX8QXP_ENET0_RGMII_TX_CLK>, <&clk IMX8QXP_ENET0_PTP_CLK>;
 529                 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
 530                 assigned-clocks = <&clk IMX8QXP_ENET0_REF_DIV>, <&clk IMX8QXP_ENET0_PTP_CLK>;
 531                 assigned-clock-rates = <125000000>, <125000000>;
 532                 fsl,num-tx-queues=<3>;
 533                 fsl,num-rx-queues=<3>;
 534                 power-domains = <&pd_conn_enet0>;
 535                 status = "disabled";
 536         };
 537
 538         fec2: ethernet@5b050000 {
 539                 compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
 540                 reg = <0x0 0x5b050000 0x0 0x10000>;
 541                 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 542                                 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
 543                                 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 544                                 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
 545                 clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>,
 546                         <&clk IMX8QXP_ENET1_RGMII_TX_CLK>, <&clk IMX8QXP_ENET1_PTP_CLK>;
 547                 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
 548                 assigned-clocks = <&clk IMX8QXP_ENET1_REF_DIV>, <&clk IMX8QXP_ENET1_PTP_CLK>;
 549                 assigned-clock-rates = <125000000>, <125000000>;
 550                 fsl,num-tx-queues=<3>;
 551                 fsl,num-rx-queues=<3>;
 552                 power-domains = <&pd_conn_enet1>;
 553                 status = "disabled";
 554         };
 555
 556         tsens: thermal-sensor {
 557                 compatible = "nxp,imx8qxp-sc-tsens";
 558                 /* number of the temp sensor on the chip */
 559                 tsens-num = <2>;
 560                 #thermal-sensor-cells = <1>;
 561         };
 562
 563         thermal_zones: thermal-zones {
 564                 /* cpu thermal */
 565                 cpu-thermal0 {
 566                         polling-delay-passive = <250>;
 567                         polling-delay = <2000>;
 568                         /*the slope and offset of the temp sensor */
 569                         thermal-sensors = <&tsens 0>;
 570                         trips {
 571                                 cpu_alert0: trip0 {
 572                                         temperature = <107000>;
 573                                         hysteresis = <2000>;
 574                                         type = "passive";
 575                                 };
 576                                 cpu_crit0: trip1 {
 577                                         temperature = <127000>;
 578                                         hysteresis = <2000>;
 579                                         type = "critical";
 580                                 };
 581                         };
 582                         cooling-maps {
 583                                 map0 {
 584                                         trip = <&cpu_alert0>;
 585                                         cooling-device =
 586                                         <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 587                                 };
 588                         };
 589                 };
 590
 591                 drc-thermal0 {
 592                         polling-delay-passive = <250>;
 593                         polling-delay = <2000>;
 594                         thermal-sensors = <&tsens 1>;
 595                         status = "disabled";
 596                         trips {
 597                                 drc_alert0: trip0 {
 598                                         temperature = <107000>;
 599                                         hysteresis = <2000>;
 600                                         type = "passive";
 601                                 };
 602                                 drc_crit0: trip1 {
 603                                         temperature = <127000>;
 604                                         hysteresis = <2000>;
 605                                         type = "critical";
 606                                 };
 607                         };
 608                 };
 609         };
 610 };
 611
 612 &A35_0 {
 613         clocks = <&clk IMX8QXP_A35_DIV>;
 614 };
 615
 616 /delete-node/ &A35_2;
 617 /delete-node/ &A35_3;