arch/arm/dts/fsl-imx8-ca35.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #include <dt-bindings/clock/imx8qxp-clock.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8
   9 /{
  10         cpus {
  11                 #address-cells = <2>;
  12                 #size-cells = <0>;
  13
  14                 /* We have 1 clusters having 4 Cortex-A35 cores */
  15                 A35_0: cpu@0 {
  16                         device_type = "cpu";
  17                         compatible = "arm,cortex-a35";
  18                         reg = <0x0 0x0>;
  19                         enable-method = "psci";
  20                         next-level-cache = <&A35_L2>;
  21                         #cooling-cells = <2>;
  22                 };
  23
  24                 A35_1: cpu@1 {
  25                         device_type = "cpu";
  26                         compatible = "arm,cortex-a35";
  27                         reg = <0x0 0x1>;
  28                         enable-method = "psci";
  29                         next-level-cache = <&A35_L2>;
  30                         #cooling-cells = <2>;
  31                 };
  32
  33                 A35_2: cpu@2 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a35";
  36                         reg = <0x0 0x2>;
  37                         enable-method = "psci";
  38                         next-level-cache = <&A35_L2>;
  39                         #cooling-cells = <2>;
  40                 };
  41
  42                 A35_3: cpu@3 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a35";
  45                         reg = <0x0 0x3>;
  46                         enable-method = "psci";
  47                         next-level-cache = <&A35_L2>;
  48                         #cooling-cells = <2>;
  49                 };
  50
  51                 A35_L2: l2-cache0 {
  52                         compatible = "cache";
  53                 };
  54         };
  55
  56         pmu {
  57                 compatible = "arm,armv8-pmuv3";
  58                 interrupts = <GIC_PPI 7
  59                         (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
  60                 interrupt-affinity = <&A35_0>, <&A35_1>, <&A35_2>, <&A35_3>;
  61         };
  62
  63         psci {
  64                 compatible = "arm,psci-1.0";
  65                 method = "smc";
  66                 cpu_suspend   = <0xc4000001>;
  67                 cpu_off       = <0xc4000002>;
  68                 cpu_on        = <0xc4000003>;
  69         };
  70 };