arch/arm/dts/fsl-imx8-ca35.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #include <dt-bindings/clock/imx8qxp-clock.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8
   9 /{
  10         cpus {
  11                 #address-cells = <2>;
  12                 #size-cells = <0>;
  13
  14                 /* We have 1 clusters having 4 Cortex-A35 cores */
  15                 A35_0: cpu@0 {
  16                         device_type = "cpu";
  17                         compatible = "arm,cortex-a35";
  18                         reg = <0x0 0x0>;
  19                         enable-method = "psci";
  20                         next-level-cache = <&A35_L2>;
  21                 };
  22
  23                 A35_1: cpu@1 {
  24                         device_type = "cpu";
  25                         compatible = "arm,cortex-a35";
  26                         reg = <0x0 0x1>;
  27                         enable-method = "psci";
  28                         next-level-cache = <&A35_L2>;
  29                 };
  30
  31                 A35_2: cpu@2 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a35";
  34                         reg = <0x0 0x2>;
  35                         enable-method = "psci";
  36                         next-level-cache = <&A35_L2>;
  37                 };
  38
  39                 A35_3: cpu@3 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a35";
  42                         reg = <0x0 0x3>;
  43                         enable-method = "psci";
  44                         next-level-cache = <&A35_L2>;
  45                 };
  46
  47                 A35_L2: l2-cache0 {
  48                         compatible = "cache";
  49                 };
  50         };
  51
  52         pmu {
  53                 compatible = "arm,armv8-pmuv3";
  54                 interrupts = <GIC_PPI 7
  55                         (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
  56                 interrupt-affinity = <&A35_0>, <&A35_1>, <&A35_2>, <&A35_3>;
  57         };
  58
  59         psci {
  60                 compatible = "arm,psci-1.0";
  61                 method = "smc";
  62                 cpu_suspend   = <0xc4000001>;
  63                 cpu_off       = <0xc4000002>;
  64                 cpu_on        = <0xc4000003>;
  65         };
  66 };