arch/arm/dts/exynos4210.dtsi

   1 /*
   2  * Samsung's Exynos4210 SoC device tree source
   3  *
   4  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  * Copyright (c) 2010-2011 Linaro Ltd.
   7  *              www.linaro.org
   8  *
   9  * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
  10  * based board files can include this file and provide values for board specfic
  11  * bindings.
  12  *
  13  * Note: This file does not include device nodes for all the controllers in
  14  * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
  15  * nodes can be added to this file.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20 */
  21
  22 #include "exynos4.dtsi"
  23 #include "exynos4210-pinctrl.dtsi"
  24 #include "exynos4210-pinctrl-uboot.dtsi"
  25
  26 / {
  27         compatible = "samsung,exynos4210";
  28
  29         aliases {
  30                 pinctrl0 = &pinctrl_0;
  31                 pinctrl1 = &pinctrl_1;
  32                 pinctrl2 = &pinctrl_2;
  33         };
  34
  35         pd_lcd1: lcd1-power-domain@10023CA0 {
  36                 compatible = "samsung,exynos4210-pd";
  37                 reg = <0x10023CA0 0x20>;
  38         };
  39
  40         gic: interrupt-controller@10490000 {
  41                 cpu-offset = <0x8000>;
  42         };
  43
  44         mct@10050000 {
  45                 compatible = "samsung,exynos4210-mct";
  46                 reg = <0x10050000 0x800>;
  47                 interrupt-parent = <&mct_map>;
  48                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
  49                 clocks = <&clock 3>, <&clock 344>;
  50                 clock-names = "fin_pll", "mct";
  51
  52                 mct_map: mct-map {
  53                         #interrupt-cells = <1>;
  54                         #address-cells = <0>;
  55                         #size-cells = <0>;
  56                         interrupt-map = <0 &gic 0 57 0>,
  57                                         <1 &gic 0 69 0>,
  58                                         <2 &combiner 12 6>,
  59                                         <3 &combiner 12 7>,
  60                                         <4 &gic 0 42 0>,
  61                                         <5 &gic 0 48 0>;
  62                 };
  63         };
  64
  65         clock: clock-controller@10030000 {
  66                 compatible = "samsung,exynos4210-clock";
  67                 reg = <0x10030000 0x20000>;
  68                 #clock-cells = <1>;
  69         };
  70
  71         pmu {
  72                 compatible = "arm,cortex-a9-pmu";
  73                 interrupt-parent = <&combiner>;
  74                 interrupts = <2 2>, <3 2>;
  75         };
  76
  77         pinctrl_0: pinctrl@11400000 {
  78                 compatible = "samsung,exynos4210-pinctrl";
  79                 reg = <0x11400000 0x1000>;
  80                 interrupt-parent = <&gic>;
  81                 interrupts = <0 47 0>;
  82         };
  83
  84         pinctrl_1: pinctrl@11000000 {
  85                 compatible = "samsung,exynos4210-pinctrl";
  86                 reg = <0x11000000 0x1000>;
  87                 interrupt-parent = <&gic>;
  88                 interrupts = <0 46 0>;
  89
  90                 wakup_eint: wakeup-interrupt-controller {
  91                         compatible = "samsung,exynos4210-wakeup-eint";
  92                         interrupt-parent = <&gic>;
  93                         interrupts = <0 32 0>;
  94                 };
  95         };
  96
  97         pinctrl_2: pinctrl@03860000 {
  98                 compatible = "samsung,exynos4210-pinctrl";
  99                 reg = <0x03860000 0x1000>;
 100         };
 101
 102         tmu@100C0000 {
 103                 compatible = "samsung,exynos4210-tmu";
 104                 interrupt-parent = <&combiner>;
 105                 reg = <0x100C0000 0x100>;
 106                 interrupts = <2 4>;
 107                 clocks = <&clock 383>;
 108                 clock-names = "tmu_apbif";
 109                 status = "disabled";
 110         };
 111
 112         g2d@12800000 {
 113                 compatible = "samsung,s5pv210-g2d";
 114                 reg = <0x12800000 0x1000>;
 115                 interrupt-parent = <&gic>;
 116                 interrupts = <0 89 0>;
 117                 clocks = <&clock 177>, <&clock 277>;
 118                 clock-names = "sclk_fimg2d", "fimg2d";
 119                 status = "disabled";
 120         };
 121
 122         camera {
 123                 clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>;
 124                 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
 125
 126                 fimc_0: fimc@11800000 {
 127                         samsung,pix-limits = <4224 8192 1920 4224>;
 128                         samsung,mainscaler-ext;
 129                         samsung,cam-if;
 130                 };
 131
 132                 fimc_1: fimc@11810000 {
 133                         samsung,pix-limits = <4224 8192 1920 4224>;
 134                         samsung,mainscaler-ext;
 135                         samsung,cam-if;
 136                 };
 137
 138                 fimc_2: fimc@11820000 {
 139                         samsung,pix-limits = <4224 8192 1920 4224>;
 140                         samsung,mainscaler-ext;
 141                         samsung,lcd-wb;
 142                 };
 143
 144                 fimc_3: fimc@11830000 {
 145                         samsung,pix-limits = <1920 8192 1366 1920>;
 146                         samsung,rotators = <0>;
 147                         samsung,mainscaler-ext;
 148                         samsung,lcd-wb;
 149                 };
 150         };
 151 };
 152
 153 &combiner {
 154         samsung,combiner-nr = <16>;
 155         interrupt-parent = <&gic>;
 156         interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
 157                      <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
 158                      <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
 159                      <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
 160 };