1 // SPDX-License-Identifier: GPL-2.0+
3 * Qualcomm APQ8096 based Dragonboard 820C board device tree source
5 * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
10 #include "skeleton64.dtsi"
11 #include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
14 model = "Qualcomm Technologies, Inc. DB820c";
15 compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
20 serial0 = &blsp2_uart2;
24 stdout-path = "serial0:115200n8";
28 device_type = "memory";
29 reg = <0 0x80000000 0 0xc0000000>;
37 smem_mem: smem_region@86300000 {
38 reg = <0x0 0x86300000 0x0 0x200000>;
44 compatible = "arm,psci-1.0";
49 compatible = "qcom,smem";
50 memory-region = <&smem_mem>;
56 ranges = <0 0 0 0xffffffff>;
57 compatible = "simple-bus";
59 gcc: clock-controller@300000 {
60 compatible = "qcom,gcc-msm8996";
63 #power-domain-cells = <1>;
64 reg = <0x300000 0x90000>;
67 pinctrl: qcom,tlmm@1010000 {
68 compatible = "qcom,tlmm-apq8096";
69 reg = <0x1010000 0x400000>;
72 function = "blsp_uart8";
73 pins = "GPIO_4", "GPIO_5";
74 drive-strength = <DRIVE_STRENGTH_8MA>;
79 blsp2_uart2: serial@75b0000 {
80 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
81 reg = <0x75b0000 0x1000>;
83 pinctrl-names = "uart";
84 pinctrl-0 = <&blsp8_uart>;
87 sdhc2: sdhci@74a4900 {
88 compatible = "qcom,sdhci-msm-v4";
89 reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
93 clock-frequency = <200000000>;
97 compatible = "qcom,spmi-pmic-arb";
98 reg = <0x400f800 0x200>,
100 <0x4c00000 0x400000>;
101 #address-cells = <0x1>;
105 compatible = "qcom,spmi-pmic";
107 #address-cells = <0x1>;
110 pm8994_pon: pm8994_pon@800 {
111 compatible = "qcom,pm8994-pwrkey";
115 gpio-bank-name="pm8994_key.";
118 pm8994_gpios: pm8994_gpios@c000 {
119 compatible = "qcom,pm8994-gpio";
120 reg = <0xc000 0x400>;
124 gpio-bank-name="pm8994.";
129 compatible = "qcom,spmi-pmic";
131 #address-cells = <0x1>;
139 #include "dragonboard820c-uboot.dtsi"