arch/arm/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/dra.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 #define MAX_SOURCES 400
  16
  17 / {
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         compatible = "ti,dra7xx";
  22         interrupt-parent = <&crossbar_mpu>;
  23
  24         aliases {
  25                 i2c0 = &i2c1;
  26                 i2c1 = &i2c2;
  27                 i2c2 = &i2c3;
  28                 i2c3 = &i2c4;
  29                 i2c4 = &i2c5;
  30                 serial0 = &uart1;
  31                 serial1 = &uart2;
  32                 serial2 = &uart3;
  33                 serial3 = &uart4;
  34                 serial4 = &uart5;
  35                 serial5 = &uart6;
  36                 serial6 = &uart7;
  37                 serial7 = &uart8;
  38                 serial8 = &uart9;
  39                 serial9 = &uart10;
  40                 ethernet0 = &cpsw_emac0;
  41                 ethernet1 = &cpsw_emac1;
  42                 d_can0 = &dcan1;
  43                 d_can1 = &dcan2;
  44                 spi0 = &qspi;
  45         };
  46
  47         timer {
  48                 compatible = "arm,armv7-timer";
  49                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  51                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  52                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  53                 interrupt-parent = <&gic>;
  54         };
  55
  56         gic: interrupt-controller@48211000 {
  57                 compatible = "arm,cortex-a15-gic";
  58                 interrupt-controller;
  59                 #interrupt-cells = <3>;
  60                 reg = <0x48211000 0x1000>,
  61                       <0x48212000 0x1000>,
  62                       <0x48214000 0x2000>,
  63                       <0x48216000 0x2000>;
  64                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  65                 interrupt-parent = <&gic>;
  66         };
  67
  68         wakeupgen: interrupt-controller@48281000 {
  69                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
  70                 interrupt-controller;
  71                 #interrupt-cells = <3>;
  72                 reg = <0x48281000 0x1000>;
  73                 interrupt-parent = <&gic>;
  74         };
  75
  76         /*
  77          * The soc node represents the soc top level view. It is used for IPs
  78          * that are not memory mapped in the MPU view or for the MPU itself.
  79          */
  80         soc {
  81                 compatible = "ti,omap-infra";
  82                 mpu {
  83                         compatible = "ti,omap5-mpu";
  84                         ti,hwmods = "mpu";
  85                 };
  86         };
  87
  88         /*
  89          * XXX: Use a flat representation of the SOC interconnect.
  90          * The real OMAP interconnect network is quite complex.
  91          * Since it will not bring real advantage to represent that in DT for
  92          * the moment, just use a fake OCP bus entry to represent the whole bus
  93          * hierarchy.
  94          */
  95         ocp {
  96                 compatible = "ti,dra7-l3-noc", "simple-bus";
  97                 #address-cells = <1>;
  98                 #size-cells = <1>;
  99                 ranges;
 100                 ti,hwmods = "l3_main_1", "l3_main_2";
 101                 reg = <0x44000000 0x1000000>,
 102                       <0x45000000 0x1000>;
 103                 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 104                                       <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 105
 106                 l4_cfg: l4@4a000000 {
 107                         compatible = "ti,dra7-l4-cfg", "simple-bus";
 108                         #address-cells = <1>;
 109                         #size-cells = <1>;
 110                         ranges = <0 0x4a000000 0x22c000>;
 111
 112                         scm: scm@2000 {
 113                                 compatible = "ti,dra7-scm-core", "simple-bus";
 114                                 reg = <0x2000 0x2000>;
 115                                 #address-cells = <1>;
 116                                 #size-cells = <1>;
 117                                 ranges = <0 0x2000 0x2000>;
 118
 119                                 scm_conf: scm_conf@0 {
 120                                         compatible = "syscon";
 121                                         reg = <0x0 0x1400>;
 122                                         #address-cells = <1>;
 123                                         #size-cells = <1>;
 124
 125                                         pbias_regulator: pbias_regulator {
 126                                                 compatible = "ti,pbias-omap";
 127                                                 reg = <0xe00 0x4>;
 128                                                 syscon = <&scm_conf>;
 129                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 130                                                         regulator-name = "pbias_mmc_omap5";
 131                                                         regulator-min-microvolt = <1800000>;
 132                                                         regulator-max-microvolt = <3000000>;
 133                                                 };
 134                                         };
 135
 136                                         scm_conf_clocks: clocks {
 137                                                 #address-cells = <1>;
 138                                                 #size-cells = <0>;
 139                                         };
 140                                 };
 141
 142                                 dra7_pmx_core: pinmux@1400 {
 143                                         compatible = "ti,dra7-padconf",
 144                                                      "pinctrl-single";
 145                                         reg = <0x1400 0x0464>;
 146                                         #address-cells = <1>;
 147                                         #size-cells = <0>;
 148                                         #interrupt-cells = <1>;
 149                                         interrupt-controller;
 150                                         pinctrl-single,register-width = <32>;
 151                                         pinctrl-single,function-mask = <0x3fffffff>;
 152                                 };
 153                         };
 154
 155                         cm_core_aon: cm_core_aon@5000 {
 156                                 compatible = "ti,dra7-cm-core-aon";
 157                                 reg = <0x5000 0x2000>;
 158
 159                                 cm_core_aon_clocks: clocks {
 160                                         #address-cells = <1>;
 161                                         #size-cells = <0>;
 162                                 };
 163
 164                                 cm_core_aon_clockdomains: clockdomains {
 165                                 };
 166                         };
 167
 168                         cm_core: cm_core@8000 {
 169                                 compatible = "ti,dra7-cm-core";
 170                                 reg = <0x8000 0x3000>;
 171
 172                                 cm_core_clocks: clocks {
 173                                         #address-cells = <1>;
 174                                         #size-cells = <0>;
 175                                 };
 176
 177                                 cm_core_clockdomains: clockdomains {
 178                                 };
 179                         };
 180                 };
 181
 182                 l4_wkup: l4@4ae00000 {
 183                         compatible = "ti,dra7-l4-wkup", "simple-bus";
 184                         #address-cells = <1>;
 185                         #size-cells = <1>;
 186                         ranges = <0 0x4ae00000 0x3f000>;
 187
 188                         counter32k: counter@4000 {
 189                                 compatible = "ti,omap-counter32k";
 190                                 reg = <0x4000 0x40>;
 191                                 ti,hwmods = "counter_32k";
 192                         };
 193
 194                         prm: prm@6000 {
 195                                 compatible = "ti,dra7-prm";
 196                                 reg = <0x6000 0x3000>;
 197                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 198
 199                                 prm_clocks: clocks {
 200                                         #address-cells = <1>;
 201                                         #size-cells = <0>;
 202                                 };
 203
 204                                 prm_clockdomains: clockdomains {
 205                                 };
 206                         };
 207                 };
 208
 209                 axi@0 {
 210                         compatible = "simple-bus";
 211                         #size-cells = <1>;
 212                         #address-cells = <1>;
 213                         ranges = <0x51000000 0x51000000 0x3000
 214                                   0x0        0x20000000 0x10000000>;
 215                         pcie@51000000 {
 216                                 compatible = "ti,dra7-pcie";
 217                                 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
 218                                 reg-names = "rc_dbics", "ti_conf", "config";
 219                                 interrupts = <0 232 0x4>, <0 233 0x4>;
 220                                 #address-cells = <3>;
 221                                 #size-cells = <2>;
 222                                 device_type = "pci";
 223                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 224                                           0x82000000 0 0x20013000 0x13000 0 0xffed000>;
 225                                 #interrupt-cells = <1>;
 226                                 num-lanes = <1>;
 227                                 ti,hwmods = "pcie1";
 228                                 phys = <&pcie1_phy>;
 229                                 phy-names = "pcie-phy0";
 230                                 interrupt-map-mask = <0 0 0 7>;
 231                                 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 232                                                 <0 0 0 2 &pcie1_intc 2>,
 233                                                 <0 0 0 3 &pcie1_intc 3>,
 234                                                 <0 0 0 4 &pcie1_intc 4>;
 235                                 pcie1_intc: interrupt-controller {
 236                                         interrupt-controller;
 237                                         #address-cells = <0>;
 238                                         #interrupt-cells = <1>;
 239                                 };
 240                         };
 241                 };
 242
 243                 axi@1 {
 244                         compatible = "simple-bus";
 245                         #size-cells = <1>;
 246                         #address-cells = <1>;
 247                         ranges = <0x51800000 0x51800000 0x3000
 248                                   0x0        0x30000000 0x10000000>;
 249                         status = "disabled";
 250                         pcie@51000000 {
 251                                 compatible = "ti,dra7-pcie";
 252                                 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
 253                                 reg-names = "rc_dbics", "ti_conf", "config";
 254                                 interrupts = <0 355 0x4>, <0 356 0x4>;
 255                                 #address-cells = <3>;
 256                                 #size-cells = <2>;
 257                                 device_type = "pci";
 258                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 259                                           0x82000000 0 0x30013000 0x13000 0 0xffed000>;
 260                                 #interrupt-cells = <1>;
 261                                 num-lanes = <1>;
 262                                 ti,hwmods = "pcie2";
 263                                 phys = <&pcie2_phy>;
 264                                 phy-names = "pcie-phy0";
 265                                 interrupt-map-mask = <0 0 0 7>;
 266                                 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
 267                                                 <0 0 0 2 &pcie2_intc 2>,
 268                                                 <0 0 0 3 &pcie2_intc 3>,
 269                                                 <0 0 0 4 &pcie2_intc 4>;
 270                                 pcie2_intc: interrupt-controller {
 271                                         interrupt-controller;
 272                                         #address-cells = <0>;
 273                                         #interrupt-cells = <1>;
 274                                 };
 275                         };
 276                 };
 277
 278                 bandgap: bandgap@4a0021e0 {
 279                         reg = <0x4a0021e0 0xc
 280                                 0x4a00232c 0xc
 281                                 0x4a002380 0x2c
 282                                 0x4a0023C0 0x3c
 283                                 0x4a002564 0x8
 284                                 0x4a002574 0x50>;
 285                                 compatible = "ti,dra752-bandgap";
 286                                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 287                                 #thermal-sensor-cells = <1>;
 288                 };
 289
 290                 dra7_ctrl_core: ctrl_core@4a002000 {
 291                         compatible = "syscon";
 292                         reg = <0x4a002000 0x6d0>;
 293                 };
 294
 295                 dra7_ctrl_general: tisyscon@4a002e00 {
 296                         compatible = "syscon";
 297                         reg = <0x4a002e00 0x7c>;
 298                 };
 299
 300                 sdma: dma-controller@4a056000 {
 301                         compatible = "ti,omap4430-sdma";
 302                         reg = <0x4a056000 0x1000>;
 303                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 304                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 305                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 306                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 307                         #dma-cells = <1>;
 308                         dma-channels = <32>;
 309                         dma-requests = <127>;
 310                 };
 311
 312                 gpio1: gpio@4ae10000 {
 313                         compatible = "ti,omap4-gpio";
 314                         reg = <0x4ae10000 0x200>;
 315                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 316                         ti,hwmods = "gpio1";
 317                         gpio-controller;
 318                         #gpio-cells = <2>;
 319                         interrupt-controller;
 320                         #interrupt-cells = <2>;
 321                 };
 322
 323                 gpio2: gpio@48055000 {
 324                         compatible = "ti,omap4-gpio";
 325                         reg = <0x48055000 0x200>;
 326                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 327                         ti,hwmods = "gpio2";
 328                         gpio-controller;
 329                         #gpio-cells = <2>;
 330                         interrupt-controller;
 331                         #interrupt-cells = <2>;
 332                 };
 333
 334                 gpio3: gpio@48057000 {
 335                         compatible = "ti,omap4-gpio";
 336                         reg = <0x48057000 0x200>;
 337                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 338                         ti,hwmods = "gpio3";
 339                         gpio-controller;
 340                         #gpio-cells = <2>;
 341                         interrupt-controller;
 342                         #interrupt-cells = <2>;
 343                 };
 344
 345                 gpio4: gpio@48059000 {
 346                         compatible = "ti,omap4-gpio";
 347                         reg = <0x48059000 0x200>;
 348                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 349                         ti,hwmods = "gpio4";
 350                         gpio-controller;
 351                         #gpio-cells = <2>;
 352                         interrupt-controller;
 353                         #interrupt-cells = <2>;
 354                 };
 355
 356                 gpio5: gpio@4805b000 {
 357                         compatible = "ti,omap4-gpio";
 358                         reg = <0x4805b000 0x200>;
 359                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 360                         ti,hwmods = "gpio5";
 361                         gpio-controller;
 362                         #gpio-cells = <2>;
 363                         interrupt-controller;
 364                         #interrupt-cells = <2>;
 365                 };
 366
 367                 gpio6: gpio@4805d000 {
 368                         compatible = "ti,omap4-gpio";
 369                         reg = <0x4805d000 0x200>;
 370                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 371                         ti,hwmods = "gpio6";
 372                         gpio-controller;
 373                         #gpio-cells = <2>;
 374                         interrupt-controller;
 375                         #interrupt-cells = <2>;
 376                 };
 377
 378                 gpio7: gpio@48051000 {
 379                         compatible = "ti,omap4-gpio";
 380                         reg = <0x48051000 0x200>;
 381                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 382                         ti,hwmods = "gpio7";
 383                         gpio-controller;
 384                         #gpio-cells = <2>;
 385                         interrupt-controller;
 386                         #interrupt-cells = <2>;
 387                 };
 388
 389                 gpio8: gpio@48053000 {
 390                         compatible = "ti,omap4-gpio";
 391                         reg = <0x48053000 0x200>;
 392                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 393                         ti,hwmods = "gpio8";
 394                         gpio-controller;
 395                         #gpio-cells = <2>;
 396                         interrupt-controller;
 397                         #interrupt-cells = <2>;
 398                 };
 399
 400                 uart1: serial@4806a000 {
 401                         compatible = "ti,omap4-uart";
 402                         reg = <0x4806a000 0x100>;
 403                         reg-shift = <2>;
 404                         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 405                         ti,hwmods = "uart1";
 406                         clock-frequency = <48000000>;
 407                         status = "disabled";
 408                         dmas = <&sdma 49>, <&sdma 50>;
 409                         dma-names = "tx", "rx";
 410                 };
 411
 412                 uart2: serial@4806c000 {
 413                         compatible = "ti,omap4-uart";
 414                         reg = <0x4806c000 0x100>;
 415                         reg-shift = <2>;
 416                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 417                         ti,hwmods = "uart2";
 418                         clock-frequency = <48000000>;
 419                         status = "disabled";
 420                         dmas = <&sdma 51>, <&sdma 52>;
 421                         dma-names = "tx", "rx";
 422                 };
 423
 424                 uart3: serial@48020000 {
 425                         compatible = "ti,omap4-uart";
 426                         reg = <0x48020000 0x100>;
 427                         reg-shift = <2>;
 428                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 429                         ti,hwmods = "uart3";
 430                         clock-frequency = <48000000>;
 431                         status = "disabled";
 432                         dmas = <&sdma 53>, <&sdma 54>;
 433                         dma-names = "tx", "rx";
 434                 };
 435
 436                 uart4: serial@4806e000 {
 437                         compatible = "ti,omap4-uart";
 438                         reg = <0x4806e000 0x100>;
 439                         reg-shift = <2>;
 440                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 441                         ti,hwmods = "uart4";
 442                         clock-frequency = <48000000>;
 443                         status = "disabled";
 444                         dmas = <&sdma 55>, <&sdma 56>;
 445                         dma-names = "tx", "rx";
 446                 };
 447
 448                 uart5: serial@48066000 {
 449                         compatible = "ti,omap4-uart";
 450                         reg = <0x48066000 0x100>;
 451                         reg-shift = <2>;
 452                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 453                         ti,hwmods = "uart5";
 454                         clock-frequency = <48000000>;
 455                         status = "disabled";
 456                         dmas = <&sdma 63>, <&sdma 64>;
 457                         dma-names = "tx", "rx";
 458                 };
 459
 460                 uart6: serial@48068000 {
 461                         compatible = "ti,omap4-uart";
 462                         reg = <0x48068000 0x100>;
 463                         reg-shift = <2>;
 464                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 465                         ti,hwmods = "uart6";
 466                         clock-frequency = <48000000>;
 467                         status = "disabled";
 468                         dmas = <&sdma 79>, <&sdma 80>;
 469                         dma-names = "tx", "rx";
 470                 };
 471
 472                 uart7: serial@48420000 {
 473                         compatible = "ti,omap4-uart";
 474                         reg = <0x48420000 0x100>;
 475                         reg-shift = <2>;
 476                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 477                         ti,hwmods = "uart7";
 478                         clock-frequency = <48000000>;
 479                         status = "disabled";
 480                 };
 481
 482                 uart8: serial@48422000 {
 483                         compatible = "ti,omap4-uart";
 484                         reg = <0x48422000 0x100>;
 485                         reg-shift = <2>;
 486                         interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 487                         ti,hwmods = "uart8";
 488                         clock-frequency = <48000000>;
 489                         status = "disabled";
 490                 };
 491
 492                 uart9: serial@48424000 {
 493                         compatible = "ti,omap4-uart";
 494                         reg = <0x48424000 0x100>;
 495                         reg-shift = <2>;
 496                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 497                         ti,hwmods = "uart9";
 498                         clock-frequency = <48000000>;
 499                         status = "disabled";
 500                 };
 501
 502                 uart10: serial@4ae2b000 {
 503                         compatible = "ti,omap4-uart";
 504                         reg = <0x4ae2b000 0x100>;
 505                         reg-shift = <2>;
 506                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 507                         ti,hwmods = "uart10";
 508                         clock-frequency = <48000000>;
 509                         status = "disabled";
 510                 };
 511
 512                 mailbox1: mailbox@4a0f4000 {
 513                         compatible = "ti,omap4-mailbox";
 514                         reg = <0x4a0f4000 0x200>;
 515                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 516                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 517                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 518                         ti,hwmods = "mailbox1";
 519                         #mbox-cells = <1>;
 520                         ti,mbox-num-users = <3>;
 521                         ti,mbox-num-fifos = <8>;
 522                         status = "disabled";
 523                 };
 524
 525                 mailbox2: mailbox@4883a000 {
 526                         compatible = "ti,omap4-mailbox";
 527                         reg = <0x4883a000 0x200>;
 528                         interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 529                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 530                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 531                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 532                         ti,hwmods = "mailbox2";
 533                         #mbox-cells = <1>;
 534                         ti,mbox-num-users = <4>;
 535                         ti,mbox-num-fifos = <12>;
 536                         status = "disabled";
 537                 };
 538
 539                 mailbox3: mailbox@4883c000 {
 540                         compatible = "ti,omap4-mailbox";
 541                         reg = <0x4883c000 0x200>;
 542                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 543                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 544                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 545                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
 546                         ti,hwmods = "mailbox3";
 547                         #mbox-cells = <1>;
 548                         ti,mbox-num-users = <4>;
 549                         ti,mbox-num-fifos = <12>;
 550                         status = "disabled";
 551                 };
 552
 553                 mailbox4: mailbox@4883e000 {
 554                         compatible = "ti,omap4-mailbox";
 555                         reg = <0x4883e000 0x200>;
 556                         interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 557                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 558                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 559                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 560                         ti,hwmods = "mailbox4";
 561                         #mbox-cells = <1>;
 562                         ti,mbox-num-users = <4>;
 563                         ti,mbox-num-fifos = <12>;
 564                         status = "disabled";
 565                 };
 566
 567                 mailbox5: mailbox@48840000 {
 568                         compatible = "ti,omap4-mailbox";
 569                         reg = <0x48840000 0x200>;
 570                         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 571                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 572                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 573                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 574                         ti,hwmods = "mailbox5";
 575                         #mbox-cells = <1>;
 576                         ti,mbox-num-users = <4>;
 577                         ti,mbox-num-fifos = <12>;
 578                         status = "disabled";
 579                 };
 580
 581                 mailbox6: mailbox@48842000 {
 582                         compatible = "ti,omap4-mailbox";
 583                         reg = <0x48842000 0x200>;
 584                         interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 585                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 586                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 587                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 588                         ti,hwmods = "mailbox6";
 589                         #mbox-cells = <1>;
 590                         ti,mbox-num-users = <4>;
 591                         ti,mbox-num-fifos = <12>;
 592                         status = "disabled";
 593                 };
 594
 595                 mailbox7: mailbox@48844000 {
 596                         compatible = "ti,omap4-mailbox";
 597                         reg = <0x48844000 0x200>;
 598                         interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 599                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 600                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 601                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
 602                         ti,hwmods = "mailbox7";
 603                         #mbox-cells = <1>;
 604                         ti,mbox-num-users = <4>;
 605                         ti,mbox-num-fifos = <12>;
 606                         status = "disabled";
 607                 };
 608
 609                 mailbox8: mailbox@48846000 {
 610                         compatible = "ti,omap4-mailbox";
 611                         reg = <0x48846000 0x200>;
 612                         interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 613                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 614                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
 615                                      <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
 616                         ti,hwmods = "mailbox8";
 617                         #mbox-cells = <1>;
 618                         ti,mbox-num-users = <4>;
 619                         ti,mbox-num-fifos = <12>;
 620                         status = "disabled";
 621                 };
 622
 623                 mailbox9: mailbox@4885e000 {
 624                         compatible = "ti,omap4-mailbox";
 625                         reg = <0x4885e000 0x200>;
 626                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 627                                      <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
 628                                      <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
 629                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 630                         ti,hwmods = "mailbox9";
 631                         #mbox-cells = <1>;
 632                         ti,mbox-num-users = <4>;
 633                         ti,mbox-num-fifos = <12>;
 634                         status = "disabled";
 635                 };
 636
 637                 mailbox10: mailbox@48860000 {
 638                         compatible = "ti,omap4-mailbox";
 639                         reg = <0x48860000 0x200>;
 640                         interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
 641                                      <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
 642                                      <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
 643                                      <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 644                         ti,hwmods = "mailbox10";
 645                         #mbox-cells = <1>;
 646                         ti,mbox-num-users = <4>;
 647                         ti,mbox-num-fifos = <12>;
 648                         status = "disabled";
 649                 };
 650
 651                 mailbox11: mailbox@48862000 {
 652                         compatible = "ti,omap4-mailbox";
 653                         reg = <0x48862000 0x200>;
 654                         interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
 655                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
 656                                      <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
 657                                      <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
 658                         ti,hwmods = "mailbox11";
 659                         #mbox-cells = <1>;
 660                         ti,mbox-num-users = <4>;
 661                         ti,mbox-num-fifos = <12>;
 662                         status = "disabled";
 663                 };
 664
 665                 mailbox12: mailbox@48864000 {
 666                         compatible = "ti,omap4-mailbox";
 667                         reg = <0x48864000 0x200>;
 668                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 669                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 670                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 671                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
 672                         ti,hwmods = "mailbox12";
 673                         #mbox-cells = <1>;
 674                         ti,mbox-num-users = <4>;
 675                         ti,mbox-num-fifos = <12>;
 676                         status = "disabled";
 677                 };
 678
 679                 mailbox13: mailbox@48802000 {
 680                         compatible = "ti,omap4-mailbox";
 681                         reg = <0x48802000 0x200>;
 682                         interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
 683                                      <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 684                                      <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
 685                                      <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
 686                         ti,hwmods = "mailbox13";
 687                         #mbox-cells = <1>;
 688                         ti,mbox-num-users = <4>;
 689                         ti,mbox-num-fifos = <12>;
 690                         status = "disabled";
 691                 };
 692
 693                 timer1: timer@4ae18000 {
 694                         compatible = "ti,omap5430-timer";
 695                         reg = <0x4ae18000 0x80>;
 696                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 697                         ti,hwmods = "timer1";
 698                         ti,timer-alwon;
 699                 };
 700
 701                 timer2: timer@48032000 {
 702                         compatible = "ti,omap5430-timer";
 703                         reg = <0x48032000 0x80>;
 704                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 705                         ti,hwmods = "timer2";
 706                 };
 707
 708                 timer3: timer@48034000 {
 709                         compatible = "ti,omap5430-timer";
 710                         reg = <0x48034000 0x80>;
 711                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 712                         ti,hwmods = "timer3";
 713                 };
 714
 715                 timer4: timer@48036000 {
 716                         compatible = "ti,omap5430-timer";
 717                         reg = <0x48036000 0x80>;
 718                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 719                         ti,hwmods = "timer4";
 720                 };
 721
 722                 timer5: timer@48820000 {
 723                         compatible = "ti,omap5430-timer";
 724                         reg = <0x48820000 0x80>;
 725                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 726                         ti,hwmods = "timer5";
 727                 };
 728
 729                 timer6: timer@48822000 {
 730                         compatible = "ti,omap5430-timer";
 731                         reg = <0x48822000 0x80>;
 732                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 733                         ti,hwmods = "timer6";
 734                 };
 735
 736                 timer7: timer@48824000 {
 737                         compatible = "ti,omap5430-timer";
 738                         reg = <0x48824000 0x80>;
 739                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 740                         ti,hwmods = "timer7";
 741                 };
 742
 743                 timer8: timer@48826000 {
 744                         compatible = "ti,omap5430-timer";
 745                         reg = <0x48826000 0x80>;
 746                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 747                         ti,hwmods = "timer8";
 748                 };
 749
 750                 timer9: timer@4803e000 {
 751                         compatible = "ti,omap5430-timer";
 752                         reg = <0x4803e000 0x80>;
 753                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 754                         ti,hwmods = "timer9";
 755                 };
 756
 757                 timer10: timer@48086000 {
 758                         compatible = "ti,omap5430-timer";
 759                         reg = <0x48086000 0x80>;
 760                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 761                         ti,hwmods = "timer10";
 762                 };
 763
 764                 timer11: timer@48088000 {
 765                         compatible = "ti,omap5430-timer";
 766                         reg = <0x48088000 0x80>;
 767                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 768                         ti,hwmods = "timer11";
 769                 };
 770
 771                 timer13: timer@48828000 {
 772                         compatible = "ti,omap5430-timer";
 773                         reg = <0x48828000 0x80>;
 774                         interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 775                         ti,hwmods = "timer13";
 776                         status = "disabled";
 777                 };
 778
 779                 timer14: timer@4882a000 {
 780                         compatible = "ti,omap5430-timer";
 781                         reg = <0x4882a000 0x80>;
 782                         interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 783                         ti,hwmods = "timer14";
 784                         status = "disabled";
 785                 };
 786
 787                 timer15: timer@4882c000 {
 788                         compatible = "ti,omap5430-timer";
 789                         reg = <0x4882c000 0x80>;
 790                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 791                         ti,hwmods = "timer15";
 792                         status = "disabled";
 793                 };
 794
 795                 timer16: timer@4882e000 {
 796                         compatible = "ti,omap5430-timer";
 797                         reg = <0x4882e000 0x80>;
 798                         interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
 799                         ti,hwmods = "timer16";
 800                         status = "disabled";
 801                 };
 802
 803                 wdt2: wdt@4ae14000 {
 804                         compatible = "ti,omap3-wdt";
 805                         reg = <0x4ae14000 0x80>;
 806                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 807                         ti,hwmods = "wd_timer2";
 808                 };
 809
 810                 hwspinlock: spinlock@4a0f6000 {
 811                         compatible = "ti,omap4-hwspinlock";
 812                         reg = <0x4a0f6000 0x1000>;
 813                         ti,hwmods = "spinlock";
 814                         #hwlock-cells = <1>;
 815                 };
 816
 817                 dmm@4e000000 {
 818                         compatible = "ti,omap5-dmm";
 819                         reg = <0x4e000000 0x800>;
 820                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 821                         ti,hwmods = "dmm";
 822                 };
 823
 824                 i2c1: i2c@48070000 {
 825                         compatible = "ti,omap4-i2c";
 826                         reg = <0x48070000 0x100>;
 827                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 828                         #address-cells = <1>;
 829                         #size-cells = <0>;
 830                         ti,hwmods = "i2c1";
 831                         status = "disabled";
 832                 };
 833
 834                 i2c2: i2c@48072000 {
 835                         compatible = "ti,omap4-i2c";
 836                         reg = <0x48072000 0x100>;
 837                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 838                         #address-cells = <1>;
 839                         #size-cells = <0>;
 840                         ti,hwmods = "i2c2";
 841                         status = "disabled";
 842                 };
 843
 844                 i2c3: i2c@48060000 {
 845                         compatible = "ti,omap4-i2c";
 846                         reg = <0x48060000 0x100>;
 847                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 848                         #address-cells = <1>;
 849                         #size-cells = <0>;
 850                         ti,hwmods = "i2c3";
 851                         status = "disabled";
 852                 };
 853
 854                 i2c4: i2c@4807a000 {
 855                         compatible = "ti,omap4-i2c";
 856                         reg = <0x4807a000 0x100>;
 857                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 858                         #address-cells = <1>;
 859                         #size-cells = <0>;
 860                         ti,hwmods = "i2c4";
 861                         status = "disabled";
 862                 };
 863
 864                 i2c5: i2c@4807c000 {
 865                         compatible = "ti,omap4-i2c";
 866                         reg = <0x4807c000 0x100>;
 867                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 868                         #address-cells = <1>;
 869                         #size-cells = <0>;
 870                         ti,hwmods = "i2c5";
 871                         status = "disabled";
 872                 };
 873
 874                 mmc1: mmc@4809c000 {
 875                         compatible = "ti,omap4-hsmmc";
 876                         reg = <0x4809c000 0x400>;
 877                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 878                         ti,hwmods = "mmc1";
 879                         ti,dual-volt;
 880                         ti,needs-special-reset;
 881                         dmas = <&sdma 61>, <&sdma 62>;
 882                         dma-names = "tx", "rx";
 883                         status = "disabled";
 884                         pbias-supply = <&pbias_mmc_reg>;
 885                 };
 886
 887                 mmc2: mmc@480b4000 {
 888                         compatible = "ti,omap4-hsmmc";
 889                         reg = <0x480b4000 0x400>;
 890                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 891                         ti,hwmods = "mmc2";
 892                         ti,needs-special-reset;
 893                         dmas = <&sdma 47>, <&sdma 48>;
 894                         dma-names = "tx", "rx";
 895                         status = "disabled";
 896                 };
 897
 898                 mmc3: mmc@480ad000 {
 899                         compatible = "ti,omap4-hsmmc";
 900                         reg = <0x480ad000 0x400>;
 901                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 902                         ti,hwmods = "mmc3";
 903                         ti,needs-special-reset;
 904                         dmas = <&sdma 77>, <&sdma 78>;
 905                         dma-names = "tx", "rx";
 906                         status = "disabled";
 907                 };
 908
 909                 mmc4: mmc@480d1000 {
 910                         compatible = "ti,omap4-hsmmc";
 911                         reg = <0x480d1000 0x400>;
 912                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 913                         ti,hwmods = "mmc4";
 914                         ti,needs-special-reset;
 915                         dmas = <&sdma 57>, <&sdma 58>;
 916                         dma-names = "tx", "rx";
 917                         status = "disabled";
 918                 };
 919
 920                 abb_mpu: regulator-abb-mpu {
 921                         compatible = "ti,abb-v3";
 922                         regulator-name = "abb_mpu";
 923                         #address-cells = <0>;
 924                         #size-cells = <0>;
 925                         clocks = <&sys_clkin1>;
 926                         ti,settling-time = <50>;
 927                         ti,clock-cycles = <16>;
 928
 929                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
 930                               <0x4ae06014 0x4>, <0x4a003b20 0xc>,
 931                               <0x4ae0c158 0x4>;
 932                         reg-names = "setup-address", "control-address",
 933                                     "int-address", "efuse-address",
 934                                     "ldo-address";
 935                         ti,tranxdone-status-mask = <0x80>;
 936                         /* LDOVBBMPU_FBB_MUX_CTRL */
 937                         ti,ldovbb-override-mask = <0x400>;
 938                         /* LDOVBBMPU_FBB_VSET_OUT */
 939                         ti,ldovbb-vset-mask = <0x1F>;
 940
 941                         /*
 942                          * NOTE: only FBB mode used but actual vset will
 943                          * determine final biasing
 944                          */
 945                         ti,abb_info = <
 946                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 947                         1060000         0       0x0     0 0x02000000 0x01F00000
 948                         1160000         0       0x4     0 0x02000000 0x01F00000
 949                         1210000         0       0x8     0 0x02000000 0x01F00000
 950                         >;
 951                 };
 952
 953                 abb_ivahd: regulator-abb-ivahd {
 954                         compatible = "ti,abb-v3";
 955                         regulator-name = "abb_ivahd";
 956                         #address-cells = <0>;
 957                         #size-cells = <0>;
 958                         clocks = <&sys_clkin1>;
 959                         ti,settling-time = <50>;
 960                         ti,clock-cycles = <16>;
 961
 962                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
 963                               <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
 964                               <0x4a002470 0x4>;
 965                         reg-names = "setup-address", "control-address",
 966                                     "int-address", "efuse-address",
 967                                     "ldo-address";
 968                         ti,tranxdone-status-mask = <0x40000000>;
 969                         /* LDOVBBIVA_FBB_MUX_CTRL */
 970                         ti,ldovbb-override-mask = <0x400>;
 971                         /* LDOVBBIVA_FBB_VSET_OUT */
 972                         ti,ldovbb-vset-mask = <0x1F>;
 973
 974                         /*
 975                          * NOTE: only FBB mode used but actual vset will
 976                          * determine final biasing
 977                          */
 978                         ti,abb_info = <
 979                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 980                         1055000         0       0x0     0 0x02000000 0x01F00000
 981                         1150000         0       0x4     0 0x02000000 0x01F00000
 982                         1250000         0       0x8     0 0x02000000 0x01F00000
 983                         >;
 984                 };
 985
 986                 abb_dspeve: regulator-abb-dspeve {
 987                         compatible = "ti,abb-v3";
 988                         regulator-name = "abb_dspeve";
 989                         #address-cells = <0>;
 990                         #size-cells = <0>;
 991                         clocks = <&sys_clkin1>;
 992                         ti,settling-time = <50>;
 993                         ti,clock-cycles = <16>;
 994
 995                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
 996                               <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
 997                               <0x4a00246c 0x4>;
 998                         reg-names = "setup-address", "control-address",
 999                                     "int-address", "efuse-address",
1000                                     "ldo-address";
1001                         ti,tranxdone-status-mask = <0x20000000>;
1002                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1003                         ti,ldovbb-override-mask = <0x400>;
1004                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
1005                         ti,ldovbb-vset-mask = <0x1F>;
1006
1007                         /*
1008                          * NOTE: only FBB mode used but actual vset will
1009                          * determine final biasing
1010                          */
1011                         ti,abb_info = <
1012                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1013                         1055000         0       0x0     0 0x02000000 0x01F00000
1014                         1150000         0       0x4     0 0x02000000 0x01F00000
1015                         1250000         0       0x8     0 0x02000000 0x01F00000
1016                         >;
1017                 };
1018
1019                 abb_gpu: regulator-abb-gpu {
1020                         compatible = "ti,abb-v3";
1021                         regulator-name = "abb_gpu";
1022                         #address-cells = <0>;
1023                         #size-cells = <0>;
1024                         clocks = <&sys_clkin1>;
1025                         ti,settling-time = <50>;
1026                         ti,clock-cycles = <16>;
1027
1028                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1029                               <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1030                               <0x4ae0c154 0x4>;
1031                         reg-names = "setup-address", "control-address",
1032                                     "int-address", "efuse-address",
1033                                     "ldo-address";
1034                         ti,tranxdone-status-mask = <0x10000000>;
1035                         /* LDOVBBGPU_FBB_MUX_CTRL */
1036                         ti,ldovbb-override-mask = <0x400>;
1037                         /* LDOVBBGPU_FBB_VSET_OUT */
1038                         ti,ldovbb-vset-mask = <0x1F>;
1039
1040                         /*
1041                          * NOTE: only FBB mode used but actual vset will
1042                          * determine final biasing
1043                          */
1044                         ti,abb_info = <
1045                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1046                         1090000         0       0x0     0 0x02000000 0x01F00000
1047                         1210000         0       0x4     0 0x02000000 0x01F00000
1048                         1280000         0       0x8     0 0x02000000 0x01F00000
1049                         >;
1050                 };
1051
1052                 mcspi1: spi@48098000 {
1053                         compatible = "ti,omap4-mcspi";
1054                         reg = <0x48098000 0x200>;
1055                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1056                         #address-cells = <1>;
1057                         #size-cells = <0>;
1058                         ti,hwmods = "mcspi1";
1059                         ti,spi-num-cs = <4>;
1060                         dmas = <&sdma 35>,
1061                                <&sdma 36>,
1062                                <&sdma 37>,
1063                                <&sdma 38>,
1064                                <&sdma 39>,
1065                                <&sdma 40>,
1066                                <&sdma 41>,
1067                                <&sdma 42>;
1068                         dma-names = "tx0", "rx0", "tx1", "rx1",
1069                                     "tx2", "rx2", "tx3", "rx3";
1070                         status = "disabled";
1071                 };
1072
1073                 mcspi2: spi@4809a000 {
1074                         compatible = "ti,omap4-mcspi";
1075                         reg = <0x4809a000 0x200>;
1076                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1077                         #address-cells = <1>;
1078                         #size-cells = <0>;
1079                         ti,hwmods = "mcspi2";
1080                         ti,spi-num-cs = <2>;
1081                         dmas = <&sdma 43>,
1082                                <&sdma 44>,
1083                                <&sdma 45>,
1084                                <&sdma 46>;
1085                         dma-names = "tx0", "rx0", "tx1", "rx1";
1086                         status = "disabled";
1087                 };
1088
1089                 mcspi3: spi@480b8000 {
1090                         compatible = "ti,omap4-mcspi";
1091                         reg = <0x480b8000 0x200>;
1092                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1093                         #address-cells = <1>;
1094                         #size-cells = <0>;
1095                         ti,hwmods = "mcspi3";
1096                         ti,spi-num-cs = <2>;
1097                         dmas = <&sdma 15>, <&sdma 16>;
1098                         dma-names = "tx0", "rx0";
1099                         status = "disabled";
1100                 };
1101
1102                 mcspi4: spi@480ba000 {
1103                         compatible = "ti,omap4-mcspi";
1104                         reg = <0x480ba000 0x200>;
1105                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1106                         #address-cells = <1>;
1107                         #size-cells = <0>;
1108                         ti,hwmods = "mcspi4";
1109                         ti,spi-num-cs = <1>;
1110                         dmas = <&sdma 70>, <&sdma 71>;
1111                         dma-names = "tx0", "rx0";
1112                         status = "disabled";
1113                 };
1114
1115                 qspi: qspi@4b300000 {
1116                         compatible = "ti,dra7xxx-qspi";
1117                         reg = <0x4b300000 0x100>,
1118                               <0x5c000000 0x4000000>,
1119                               <0x4a002558 0x4>;
1120                         reg-names = "qspi_base", "qspi_mmap",
1121                                     "qspi_ctrlmod";
1122                         #address-cells = <1>;
1123                         #size-cells = <0>;
1124                         ti,hwmods = "qspi";
1125                         clocks = <&qspi_gfclk_div>;
1126                         clock-names = "fck";
1127                         num-cs = <4>;
1128                         interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1129                         status = "disabled";
1130                 };
1131
1132                 omap_control_sata: control-phy@4a002374 {
1133                         compatible = "ti,control-phy-pipe3";
1134                         reg = <0x4a002374 0x4>;
1135                         reg-names = "power";
1136                         clocks = <&sys_clkin1>;
1137                         clock-names = "sysclk";
1138                 };
1139
1140                 /* OCP2SCP3 */
1141                 ocp2scp@4a090000 {
1142                         compatible = "ti,omap-ocp2scp";
1143                         #address-cells = <1>;
1144                         #size-cells = <1>;
1145                         ranges;
1146                         reg = <0x4a090000 0x20>;
1147                         ti,hwmods = "ocp2scp3";
1148                         sata_phy: phy@4A096000 {
1149                                 compatible = "ti,phy-pipe3-sata";
1150                                 reg = <0x4A096000 0x80>, /* phy_rx */
1151                                       <0x4A096400 0x64>, /* phy_tx */
1152                                       <0x4A096800 0x40>; /* pll_ctrl */
1153                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1154                                 ctrl-module = <&omap_control_sata>;
1155                                 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1156                                 clock-names = "sysclk", "refclk";
1157                                 #phy-cells = <0>;
1158                         };
1159
1160                         pcie1_phy: pciephy@4a094000 {
1161                                 compatible = "ti,phy-pipe3-pcie";
1162                                 reg = <0x4a094000 0x80>, /* phy_rx */
1163                                       <0x4a094400 0x64>; /* phy_tx */
1164                                 reg-names = "phy_rx", "phy_tx";
1165                                 ctrl-module = <&omap_control_pcie1phy>;
1166                                 clocks = <&dpll_pcie_ref_ck>,
1167                                          <&dpll_pcie_ref_m2ldo_ck>,
1168                                          <&optfclk_pciephy1_32khz>,
1169                                          <&optfclk_pciephy1_clk>,
1170                                          <&optfclk_pciephy1_div_clk>,
1171                                          <&optfclk_pciephy_div>;
1172                                 clock-names = "dpll_ref", "dpll_ref_m2",
1173                                               "wkupclk", "refclk",
1174                                               "div-clk", "phy-div";
1175                                 #phy-cells = <0>;
1176                         };
1177
1178                         pcie2_phy: pciephy@4a095000 {
1179                                 compatible = "ti,phy-pipe3-pcie";
1180                                 reg = <0x4a095000 0x80>, /* phy_rx */
1181                                       <0x4a095400 0x64>; /* phy_tx */
1182                                 reg-names = "phy_rx", "phy_tx";
1183                                 ctrl-module = <&omap_control_pcie2phy>;
1184                                 clocks = <&dpll_pcie_ref_ck>,
1185                                          <&dpll_pcie_ref_m2ldo_ck>,
1186                                          <&optfclk_pciephy2_32khz>,
1187                                          <&optfclk_pciephy2_clk>,
1188                                          <&optfclk_pciephy2_div_clk>,
1189                                          <&optfclk_pciephy_div>;
1190                                 clock-names = "dpll_ref", "dpll_ref_m2",
1191                                               "wkupclk", "refclk",
1192                                               "div-clk", "phy-div";
1193                                 #phy-cells = <0>;
1194                                 status = "disabled";
1195                         };
1196                 };
1197
1198                 sata: sata@4a141100 {
1199                         compatible = "snps,dwc-ahci";
1200                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1201                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1202                         phys = <&sata_phy>;
1203                         phy-names = "sata-phy";
1204                         clocks = <&sata_ref_clk>;
1205                         ti,hwmods = "sata";
1206                 };
1207
1208                 omap_control_pcie1phy: control-phy@0x4a003c40 {
1209                         compatible = "ti,control-phy-pcie";
1210                         reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1211                         reg-names = "power", "control_sma", "pcie_pcs";
1212                         clocks = <&sys_clkin1>;
1213                         clock-names = "sysclk";
1214                 };
1215
1216                 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1217                         compatible = "ti,control-phy-pcie";
1218                         reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1219                         reg-names = "power", "control_sma", "pcie_pcs";
1220                         clocks = <&sys_clkin1>;
1221                         clock-names = "sysclk";
1222                         status = "disabled";
1223                 };
1224
1225                 rtc: rtc@48838000 {
1226                         compatible = "ti,am3352-rtc";
1227                         reg = <0x48838000 0x100>;
1228                         interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1229                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1230                         ti,hwmods = "rtcss";
1231                         clocks = <&sys_32k_ck>;
1232                 };
1233
1234                 omap_control_usb2phy1: control-phy@4a002300 {
1235                         compatible = "ti,control-phy-usb2";
1236                         reg = <0x4a002300 0x4>;
1237                         reg-names = "power";
1238                 };
1239
1240                 omap_control_usb3phy1: control-phy@4a002370 {
1241                         compatible = "ti,control-phy-pipe3";
1242                         reg = <0x4a002370 0x4>;
1243                         reg-names = "power";
1244                 };
1245
1246                 omap_control_usb2phy2: control-phy@0x4a002e74 {
1247                         compatible = "ti,control-phy-usb2-dra7";
1248                         reg = <0x4a002e74 0x4>;
1249                         reg-names = "power";
1250                 };
1251
1252                 /* OCP2SCP1 */
1253                 ocp2scp@4a080000 {
1254                         compatible = "ti,omap-ocp2scp";
1255                         #address-cells = <1>;
1256                         #size-cells = <1>;
1257                         ranges;
1258                         reg = <0x4a080000 0x20>;
1259                         ti,hwmods = "ocp2scp1";
1260
1261                         usb2_phy1: phy@4a084000 {
1262                                 compatible = "ti,omap-usb2";
1263                                 reg = <0x4a084000 0x400>;
1264                                 ctrl-module = <&omap_control_usb2phy1>;
1265                                 clocks = <&usb_phy1_always_on_clk32k>,
1266                                          <&usb_otg_ss1_refclk960m>;
1267                                 clock-names =   "wkupclk",
1268                                                 "refclk";
1269                                 #phy-cells = <0>;
1270                         };
1271
1272                         usb2_phy2: phy@4a085000 {
1273                                 compatible = "ti,omap-usb2";
1274                                 reg = <0x4a085000 0x400>;
1275                                 ctrl-module = <&omap_control_usb2phy2>;
1276                                 clocks = <&usb_phy2_always_on_clk32k>,
1277                                          <&usb_otg_ss2_refclk960m>;
1278                                 clock-names =   "wkupclk",
1279                                                 "refclk";
1280                                 #phy-cells = <0>;
1281                         };
1282
1283                         usb3_phy1: phy@4a084400 {
1284                                 compatible = "ti,omap-usb3";
1285                                 reg = <0x4a084400 0x80>,
1286                                       <0x4a084800 0x64>,
1287                                       <0x4a084c00 0x40>;
1288                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1289                                 ctrl-module = <&omap_control_usb3phy1>;
1290                                 clocks = <&usb_phy3_always_on_clk32k>,
1291                                          <&sys_clkin1>,
1292                                          <&usb_otg_ss1_refclk960m>;
1293                                 clock-names =   "wkupclk",
1294                                                 "sysclk",
1295                                                 "refclk";
1296                                 #phy-cells = <0>;
1297                         };
1298                 };
1299
1300                 omap_dwc3_1: omap_dwc3_1@48880000 {
1301                         compatible = "ti,dwc3";
1302                         ti,hwmods = "usb_otg_ss1";
1303                         reg = <0x48880000 0x10000>;
1304                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1305                         #address-cells = <1>;
1306                         #size-cells = <1>;
1307                         utmi-mode = <2>;
1308                         ranges;
1309                         usb1: usb@48890000 {
1310                                 compatible = "snps,dwc3";
1311                                 reg = <0x48890000 0x17000>;
1312                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1313                                 phys = <&usb2_phy1>, <&usb3_phy1>;
1314                                 phy-names = "usb2-phy", "usb3-phy";
1315                                 tx-fifo-resize;
1316                                 maximum-speed = "super-speed";
1317                                 dr_mode = "otg";
1318                                 snps,dis_u3_susphy_quirk;
1319                                 snps,dis_u2_susphy_quirk;
1320                         };
1321                 };
1322
1323                 omap_dwc3_2: omap_dwc3_2@488c0000 {
1324                         compatible = "ti,dwc3";
1325                         ti,hwmods = "usb_otg_ss2";
1326                         reg = <0x488c0000 0x10000>;
1327                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1328                         #address-cells = <1>;
1329                         #size-cells = <1>;
1330                         utmi-mode = <2>;
1331                         ranges;
1332                         usb2: usb@488d0000 {
1333                                 compatible = "snps,dwc3";
1334                                 reg = <0x488d0000 0x17000>;
1335                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1336                                 phys = <&usb2_phy2>;
1337                                 phy-names = "usb2-phy";
1338                                 tx-fifo-resize;
1339                                 maximum-speed = "high-speed";
1340                                 dr_mode = "otg";
1341                                 snps,dis_u3_susphy_quirk;
1342                                 snps,dis_u2_susphy_quirk;
1343                         };
1344                 };
1345
1346                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1347                 omap_dwc3_3: omap_dwc3_3@48900000 {
1348                         compatible = "ti,dwc3";
1349                         ti,hwmods = "usb_otg_ss3";
1350                         reg = <0x48900000 0x10000>;
1351                         interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1352                         #address-cells = <1>;
1353                         #size-cells = <1>;
1354                         utmi-mode = <2>;
1355                         ranges;
1356                         status = "disabled";
1357                         usb3: usb@48910000 {
1358                                 compatible = "snps,dwc3";
1359                                 reg = <0x48910000 0x17000>;
1360                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1361                                 tx-fifo-resize;
1362                                 maximum-speed = "high-speed";
1363                                 dr_mode = "otg";
1364                                 snps,dis_u3_susphy_quirk;
1365                                 snps,dis_u2_susphy_quirk;
1366                         };
1367                 };
1368
1369                 elm: elm@48078000 {
1370                         compatible = "ti,am3352-elm";
1371                         reg = <0x48078000 0xfc0>;      /* device IO registers */
1372                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1373                         ti,hwmods = "elm";
1374                         status = "disabled";
1375                 };
1376
1377                 gpmc: gpmc@50000000 {
1378                         compatible = "ti,am3352-gpmc";
1379                         ti,hwmods = "gpmc";
1380                         reg = <0x50000000 0x37c>;      /* device IO registers */
1381                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1382                         gpmc,num-cs = <8>;
1383                         gpmc,num-waitpins = <2>;
1384                         #address-cells = <2>;
1385                         #size-cells = <1>;
1386                         status = "disabled";
1387                 };
1388
1389                 atl: atl@4843c000 {
1390                         compatible = "ti,dra7-atl";
1391                         reg = <0x4843c000 0x3ff>;
1392                         ti,hwmods = "atl";
1393                         ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1394                                              <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1395                         clocks = <&atl_gfclk_mux>;
1396                         clock-names = "fck";
1397                         status = "disabled";
1398                 };
1399
1400                 crossbar_mpu: crossbar@4a002a48 {
1401                         compatible = "ti,irq-crossbar";
1402                         reg = <0x4a002a48 0x130>;
1403                         interrupt-controller;
1404                         interrupt-parent = <&wakeupgen>;
1405                         #interrupt-cells = <3>;
1406                         ti,max-irqs = <160>;
1407                         ti,max-crossbar-sources = <MAX_SOURCES>;
1408                         ti,reg-size = <2>;
1409                         ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1410                         ti,irqs-skip = <10 133 139 140>;
1411                         ti,irqs-safe-map = <0>;
1412                 };
1413
1414                 mac: ethernet@4a100000 {
1415                         compatible = "ti,cpsw";
1416                         ti,hwmods = "gmac";
1417                         clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1418                         clock-names = "fck", "cpts";
1419                         cpdma_channels = <8>;
1420                         ale_entries = <1024>;
1421                         bd_ram_size = <0x2000>;
1422                         no_bd_ram = <0>;
1423                         rx_descs = <64>;
1424                         mac_control = <0x20>;
1425                         slaves = <2>;
1426                         active_slave = <0>;
1427                         cpts_clock_mult = <0x80000000>;
1428                         cpts_clock_shift = <29>;
1429                         reg = <0x48484000 0x1000
1430                                0x48485200 0x2E00>;
1431                         #address-cells = <1>;
1432                         #size-cells = <1>;
1433                         /*
1434                          * rx_thresh_pend
1435                          * rx_pend
1436                          * tx_pend
1437                          * misc_pend
1438                          */
1439                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1440                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1441                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1442                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1443                         ranges;
1444                         status = "disabled";
1445
1446                         davinci_mdio: mdio@48485000 {
1447                                 compatible = "ti,davinci_mdio";
1448                                 #address-cells = <1>;
1449                                 #size-cells = <0>;
1450                                 ti,hwmods = "davinci_mdio";
1451                                 bus_freq = <1000000>;
1452                                 reg = <0x48485000 0x100>;
1453                         };
1454
1455                         cpsw_emac0: slave@48480200 {
1456                                 /* Filled in by U-Boot */
1457                                 mac-address = [ 00 00 00 00 00 00 ];
1458                         };
1459
1460                         cpsw_emac1: slave@48480300 {
1461                                 /* Filled in by U-Boot */
1462                                 mac-address = [ 00 00 00 00 00 00 ];
1463                         };
1464
1465                         phy_sel: cpsw-phy-sel@4a002554 {
1466                                 compatible = "ti,dra7xx-cpsw-phy-sel";
1467                                 reg= <0x4a002554 0x4>;
1468                                 reg-names = "gmii-sel";
1469                         };
1470                 };
1471
1472                 dcan1: can@481cc000 {
1473                         compatible = "ti,dra7-d_can";
1474                         ti,hwmods = "dcan1";
1475                         reg = <0x4ae3c000 0x2000>;
1476                         syscon-raminit = <&scm_conf 0x558 0>;
1477                         interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1478                         clocks = <&dcan1_sys_clk_mux>;
1479                         status = "disabled";
1480                 };
1481
1482                 dcan2: can@481d0000 {
1483                         compatible = "ti,dra7-d_can";
1484                         ti,hwmods = "dcan2";
1485                         reg = <0x48480000 0x2000>;
1486                         syscon-raminit = <&scm_conf 0x558 1>;
1487                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1488                         clocks = <&sys_clkin1>;
1489                         status = "disabled";
1490                 };
1491
1492                 dss: dss@58000000 {
1493                         compatible = "ti,dra7-dss";
1494                         /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1495                         /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1496                         status = "disabled";
1497                         ti,hwmods = "dss_core";
1498                         /* CTRL_CORE_DSS_PLL_CONTROL */
1499                         syscon-pll-ctrl = <&scm_conf 0x538>;
1500                         #address-cells = <1>;
1501                         #size-cells = <1>;
1502                         ranges;
1503
1504                         dispc@58001000 {
1505                                 compatible = "ti,dra7-dispc";
1506                                 reg = <0x58001000 0x1000>;
1507                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1508                                 ti,hwmods = "dss_dispc";
1509                                 clocks = <&dss_dss_clk>;
1510                                 clock-names = "fck";
1511                                 /* CTRL_CORE_SMA_SW_1 */
1512                                 syscon-pol = <&scm_conf 0x534>;
1513                         };
1514
1515                         hdmi: encoder@58060000 {
1516                                 compatible = "ti,dra7-hdmi";
1517                                 reg = <0x58040000 0x200>,
1518                                       <0x58040200 0x80>,
1519                                       <0x58040300 0x80>,
1520                                       <0x58060000 0x19000>;
1521                                 reg-names = "wp", "pll", "phy", "core";
1522                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1523                                 status = "disabled";
1524                                 ti,hwmods = "dss_hdmi";
1525                                 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1526                                 clock-names = "fck", "sys_clk";
1527                         };
1528                 };
1529         };
1530
1531         thermal_zones: thermal-zones {
1532                 #include "omap4-cpu-thermal.dtsi"
1533                 #include "omap5-gpu-thermal.dtsi"
1534                 #include "omap5-core-thermal.dtsi"
1535         };
1536
1537 };
1538
1539 &cpu_thermal {
1540         polling-delay = <500>; /* milliseconds */
1541 };
1542
1543 /include/ "dra7xx-clocks.dtsi"