2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include "dra74x.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
15 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
22 device_type = "memory";
23 reg = <0x80000000 0x60000000>; /* 1536 MB */
26 mmc2_3v3: fixedregulator-mmc2 {
27 compatible = "regulator-fixed";
28 regulator-name = "mmc2_3v3";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
33 extcon_usb1: extcon_usb1 {
34 compatible = "linux,extcon-usb-gpio";
35 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
38 extcon_usb2: extcon_usb2 {
39 compatible = "linux,extcon-usb-gpio";
40 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
43 vtt_fixed: fixedregulator-vtt {
44 compatible = "regulator-fixed";
45 regulator-name = "vtt_fixed";
46 regulator-min-microvolt = <1350000>;
47 regulator-max-microvolt = <1350000>;
51 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
56 pinctrl-names = "default";
57 pinctrl-0 = <&vtt_pin>;
59 vtt_pin: pinmux_vtt_pin {
60 pinctrl-single,pins = <
61 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
65 i2c1_pins: pinmux_i2c1_pins {
66 pinctrl-single,pins = <
67 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
68 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
72 i2c2_pins: pinmux_i2c2_pins {
73 pinctrl-single,pins = <
74 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
75 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
79 i2c3_pins: pinmux_i2c3_pins {
80 pinctrl-single,pins = <
81 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
82 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
86 mcspi1_pins: pinmux_mcspi1_pins {
87 pinctrl-single,pins = <
88 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
89 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
90 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
91 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
92 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
93 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
97 mcspi2_pins: pinmux_mcspi2_pins {
98 pinctrl-single,pins = <
99 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
100 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
101 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
102 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
106 uart1_pins: pinmux_uart1_pins {
107 pinctrl-single,pins = <
108 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
109 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
110 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
111 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
115 uart2_pins: pinmux_uart2_pins {
116 pinctrl-single,pins = <
117 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
118 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
119 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
120 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
124 uart3_pins: pinmux_uart3_pins {
125 pinctrl-single,pins = <
126 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
127 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
131 qspi1_pins: pinmux_qspi1_pins {
132 pinctrl-single,pins = <
133 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
134 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
135 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
136 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
137 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
138 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
139 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
140 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
141 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
142 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
146 usb1_pins: pinmux_usb1_pins {
147 pinctrl-single,pins = <
148 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
152 usb2_pins: pinmux_usb2_pins {
153 pinctrl-single,pins = <
154 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
158 nand_flash_x16: nand_flash_x16 {
159 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
160 * So NAND flash requires following switch settings:
161 * SW5.9 (GPMC_WPN) = LOW
162 * SW5.1 (NAND_BOOTn) = HIGH */
163 pinctrl-single,pins = <
164 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
165 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
166 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
167 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
168 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
169 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
170 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
171 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
172 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
173 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
174 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
175 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
176 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
177 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
178 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
179 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
180 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
181 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
182 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
183 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
184 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
185 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
189 cpsw_default: cpsw_default {
190 pinctrl-single,pins = <
192 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
193 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
194 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
195 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
196 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
197 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
198 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
199 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
200 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
201 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
202 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
203 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
206 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
207 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
208 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
209 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
210 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
211 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
212 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
213 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
214 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
215 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
216 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
217 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
222 cpsw_sleep: cpsw_sleep {
223 pinctrl-single,pins = <
254 davinci_mdio_default: davinci_mdio_default {
255 pinctrl-single,pins = <
256 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
257 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
261 davinci_mdio_sleep: davinci_mdio_sleep {
262 pinctrl-single,pins = <
268 dcan1_pins_default: dcan1_pins_default {
269 pinctrl-single,pins = <
270 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
271 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
275 dcan1_pins_sleep: dcan1_pins_sleep {
276 pinctrl-single,pins = <
277 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
278 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
285 pinctrl-names = "default";
286 pinctrl-0 = <&i2c1_pins>;
287 clock-frequency = <400000>;
289 tps659038: tps659038@58 {
290 compatible = "ti,tps659038";
294 compatible = "ti,tps659038-pmic";
297 smps123_reg: smps123 {
299 regulator-name = "smps123";
300 regulator-min-microvolt = < 850000>;
301 regulator-max-microvolt = <1250000>;
308 regulator-name = "smps45";
309 regulator-min-microvolt = < 850000>;
310 regulator-max-microvolt = <1150000>;
316 /* VDD_GPU - over VDD_SMPS6 */
317 regulator-name = "smps6";
318 regulator-min-microvolt = <850000>;
319 regulator-max-microvolt = <1250000>;
326 regulator-name = "smps7";
327 regulator-min-microvolt = <850000>;
328 regulator-max-microvolt = <1060000>;
335 regulator-name = "smps8";
336 regulator-min-microvolt = < 850000>;
337 regulator-max-microvolt = <1250000>;
344 regulator-name = "smps9";
345 regulator-min-microvolt = <1800000>;
346 regulator-max-microvolt = <1800000>;
352 /* LDO1_OUT --> SDIO */
353 regulator-name = "ldo1";
354 regulator-min-microvolt = <1800000>;
355 regulator-max-microvolt = <3300000>;
361 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
362 regulator-name = "ldo2";
363 regulator-min-microvolt = <3300000>;
364 regulator-max-microvolt = <3300000>;
371 regulator-name = "ldo3";
372 regulator-min-microvolt = <1800000>;
373 regulator-max-microvolt = <1800000>;
380 regulator-name = "ldo9";
381 regulator-min-microvolt = <1050000>;
382 regulator-max-microvolt = <1050000>;
389 regulator-name = "ldoln";
390 regulator-min-microvolt = <1800000>;
391 regulator-max-microvolt = <1800000>;
397 /* VDDA_3V_USB: VDDA_USBHS33 */
398 regulator-name = "ldousb";
399 regulator-min-microvolt = <3300000>;
400 regulator-max-microvolt = <3300000>;
407 pcf_gpio_21: gpio@21 {
408 compatible = "ti,pcf8575";
410 lines-initial-states = <0x1408>;
413 interrupt-parent = <&gpio6>;
414 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
415 interrupt-controller;
416 #interrupt-cells = <2>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&i2c2_pins>;
425 clock-frequency = <400000>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&i2c3_pins>;
432 clock-frequency = <400000>;
437 pinctrl-names = "default";
438 pinctrl-0 = <&mcspi1_pins>;
443 pinctrl-names = "default";
444 pinctrl-0 = <&mcspi2_pins>;
449 pinctrl-names = "default";
450 pinctrl-0 = <&uart1_pins>;
451 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
452 <&dra7_pmx_core 0x3e0>;
457 pinctrl-names = "default";
458 pinctrl-0 = <&uart2_pins>;
463 pinctrl-names = "default";
464 pinctrl-0 = <&uart3_pins>;
469 vmmc-supply = <&ldo1_reg>;
475 vmmc-supply = <&mmc2_3v3>;
480 cpu0-supply = <&smps123_reg>;
485 pinctrl-names = "default";
486 pinctrl-0 = <&qspi1_pins>;
488 spi-max-frequency = <48000000>;
490 compatible = "s25fl256s1";
491 spi-max-frequency = <48000000>;
493 spi-tx-bus-width = <1>;
494 spi-rx-bus-width = <4>;
497 #address-cells = <1>;
500 /* MTD partition table.
501 * The ROM checks the first four physical blocks
502 * for a valid file to boot and the flash here is
507 reg = <0x00000000 0x000010000>;
510 label = "QSPI.SPL.backup1";
511 reg = <0x00010000 0x00010000>;
514 label = "QSPI.SPL.backup2";
515 reg = <0x00020000 0x00010000>;
518 label = "QSPI.SPL.backup3";
519 reg = <0x00030000 0x00010000>;
522 label = "QSPI.u-boot";
523 reg = <0x00040000 0x00100000>;
526 label = "QSPI.u-boot-spl-os";
527 reg = <0x00140000 0x00080000>;
530 label = "QSPI.u-boot-env";
531 reg = <0x001c0000 0x00010000>;
534 label = "QSPI.u-boot-env.backup1";
535 reg = <0x001d0000 0x0010000>;
538 label = "QSPI.kernel";
539 reg = <0x001e0000 0x0800000>;
542 label = "QSPI.file-system";
543 reg = <0x009e0000 0x01620000>;
549 extcon = <&extcon_usb1>;
553 extcon = <&extcon_usb2>;
557 dr_mode = "peripheral";
558 pinctrl-names = "default";
559 pinctrl-0 = <&usb1_pins>;
564 pinctrl-names = "default";
565 pinctrl-0 = <&usb2_pins>;
574 pinctrl-names = "default";
575 pinctrl-0 = <&nand_flash_x16>;
576 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
578 reg = <0 0 4>; /* device IO registers */
579 ti,nand-ecc-opt = "bch8";
581 nand-bus-width = <16>;
582 gpmc,device-width = <2>;
583 gpmc,sync-clk-ps = <0>;
585 gpmc,cs-rd-off-ns = <80>;
586 gpmc,cs-wr-off-ns = <80>;
587 gpmc,adv-on-ns = <0>;
588 gpmc,adv-rd-off-ns = <60>;
589 gpmc,adv-wr-off-ns = <60>;
590 gpmc,we-on-ns = <10>;
591 gpmc,we-off-ns = <50>;
593 gpmc,oe-off-ns = <40>;
594 gpmc,access-ns = <40>;
595 gpmc,wr-access-ns = <80>;
596 gpmc,rd-cycle-ns = <80>;
597 gpmc,wr-cycle-ns = <80>;
598 gpmc,bus-turnaround-ns = <0>;
599 gpmc,cycle2cycle-delay-ns = <0>;
600 gpmc,clk-activation-ns = <0>;
601 gpmc,wait-monitoring-ns = <0>;
602 gpmc,wr-data-mux-bus-ns = <0>;
603 /* MTD partition table */
604 /* All SPL-* partitions are sized to minimal length
605 * which can be independently programmable. For
606 * NAND flash this is equal to size of erase-block */
607 #address-cells = <1>;
611 reg = <0x00000000 0x000020000>;
614 label = "NAND.SPL.backup1";
615 reg = <0x00020000 0x00020000>;
618 label = "NAND.SPL.backup2";
619 reg = <0x00040000 0x00020000>;
622 label = "NAND.SPL.backup3";
623 reg = <0x00060000 0x00020000>;
626 label = "NAND.u-boot-spl-os";
627 reg = <0x00080000 0x00040000>;
630 label = "NAND.u-boot";
631 reg = <0x000c0000 0x00100000>;
634 label = "NAND.u-boot-env";
635 reg = <0x001c0000 0x00020000>;
638 label = "NAND.u-boot-env.backup1";
639 reg = <0x001e0000 0x00020000>;
642 label = "NAND.kernel";
643 reg = <0x00200000 0x00800000>;
646 label = "NAND.file-system";
647 reg = <0x00a00000 0x0f600000>;
653 phy-supply = <&ldousb_reg>;
657 phy-supply = <&ldousb_reg>;
667 pinctrl-names = "default", "sleep";
668 pinctrl-0 = <&cpsw_default>;
669 pinctrl-1 = <&cpsw_sleep>;
674 phy_id = <&davinci_mdio>, <2>;
676 dual_emac_res_vlan = <1>;
680 phy_id = <&davinci_mdio>, <3>;
682 dual_emac_res_vlan = <2>;
686 pinctrl-names = "default", "sleep";
687 pinctrl-0 = <&davinci_mdio_default>;
688 pinctrl-1 = <&davinci_mdio_sleep>;
693 pinctrl-names = "default", "sleep", "active";
694 pinctrl-0 = <&dcan1_pins_sleep>;
695 pinctrl-1 = <&dcan1_pins_sleep>;
696 pinctrl-2 = <&dcan1_pins_default>;