1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
6 #include "skeleton64.dtsi"
9 compatible = "brcm,bcm6858";
19 compatible = "arm,cortex-a53", "arm,armv8";
22 next-level-cache = <&l2>;
27 compatible = "arm,cortex-a53", "arm,armv8";
30 next-level-cache = <&l2>;
35 compatible = "arm,cortex-a53", "arm,armv8";
38 next-level-cache = <&l2>;
43 compatible = "arm,cortex-a53", "arm,armv8";
46 next-level-cache = <&l2>;
57 compatible = "simple-bus";
63 periph_osc: periph-osc {
64 compatible = "fixed-clock";
66 clock-frequency = <200000000>;
70 refclk50mhz: refclk50mhz {
71 compatible = "fixed-clock";
73 clock-frequency = <50000000>;
78 compatible = "simple-bus";
83 uart0: serial@ff800640 {
84 compatible = "brcm,bcm6345-uart";
85 reg = <0x0 0xff800640 0x0 0x18>;
86 clocks = <&periph_osc>;
91 leds: led-controller@ff800800 {
92 compatible = "brcm,bcm6858-leds";
93 reg = <0x0 0xff800800 0x0 0xe4>;
98 wdt1: watchdog@ff802780 {
99 compatible = "brcm,bcm6345-wdt";
100 reg = <0x0 0xff802780 0x0 0x14>;
101 clocks = <&refclk50mhz>;
104 wdt2: watchdog@ff8027c0 {
105 compatible = "brcm,bcm6345-wdt";
106 reg = <0x0 0xff8027c0 0x0 0x14>;
107 clocks = <&refclk50mhz>;
111 compatible = "wdt-reboot";
115 gpio0: gpio-controller@0xff800500 {
116 compatible = "brcm,bcm6345-gpio";
117 reg = <0x0 0xff800500 0x0 0x4>,
118 <0x0 0xff800520 0x0 0x4>;
125 gpio1: gpio-controller@0xff800504 {
126 compatible = "brcm,bcm6345-gpio";
127 reg = <0x0 0xff800504 0x0 0x4>,
128 <0x0 0xff800524 0x0 0x4>;
135 gpio2: gpio-controller@0xff800508 {
136 compatible = "brcm,bcm6345-gpio";
137 reg = <0x0 0xff800508 0x0 0x4>,
138 <0x0 0xff800528 0x0 0x4>;
145 gpio3: gpio-controller@0xff80050c {
146 compatible = "brcm,bcm6345-gpio";
147 reg = <0x0 0xff80050c 0x0 0x4>,
148 <0x0 0xff80052c 0x0 0x4>;
155 gpio4: gpio-controller@0xff800510 {
156 compatible = "brcm,bcm6345-gpio";
157 reg = <0x0 0xff800510 0x0 0x4>,
158 <0x0 0xff800530 0x0 0x4>;
165 gpio5: gpio-controller@0xff800514 {
166 compatible = "brcm,bcm6345-gpio";
167 reg = <0x0 0xff800514 0x0 0x4>,
168 <0x0 0xff800534 0x0 0x4>;
175 gpio6: gpio-controller@0xff800518 {
176 compatible = "brcm,bcm6345-gpio";
177 reg = <0x0 0xff800518 0x0 0x4>,
178 <0x0 0xff800538 0x0 0x4>;
185 gpio7: gpio-controller@0xff80051c {
186 compatible = "brcm,bcm6345-gpio";
187 reg = <0x0 0xff80051c 0x0 0x4>,
188 <0x0 0xff80053c 0x0 0x4>;
195 nand: nand-controller@ff801800 {
196 compatible = "brcm,nand-bcm6858",
197 "brcm,brcmnand-v5.0",
199 reg-names = "nand", "nand-int-base", "nand-cache";
200 reg = <0x0 0xff801800 0x0 0x180>,
201 <0x0 0xff802000 0x0 0x10>,
202 <0x0 0xff801c00 0x0 0x200>;
203 parameter-page-big-endian = <0>;