1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com>
6 #include "skeleton64.dtsi"
9 compatible = "brcm,bcm68360";
23 compatible = "arm,cortex-a53", "arm,armv8";
26 next-level-cache = <&l2>;
31 compatible = "arm,cortex-a53", "arm,armv8";
34 next-level-cache = <&l2>;
45 compatible = "simple-bus";
51 periph_osc: periph-osc {
52 compatible = "fixed-clock";
54 clock-frequency = <200000000>;
58 hsspi_pll: hsspi-pll {
59 compatible = "fixed-factor-clock";
61 clocks = <&periph_osc>;
66 refclk50mhz: refclk50mhz {
67 compatible = "fixed-clock";
69 clock-frequency = <50000000>;
74 compatible = "simple-bus";
79 wdt1: watchdog@ff800480 {
80 compatible = "brcm,bcm6345-wdt";
81 reg = <0x0 0xff800480 0x0 0x14>;
82 clocks = <&refclk50mhz>;
85 wdt2: watchdog@ff8004c0 {
86 compatible = "brcm,bcm6345-wdt";
87 reg = <0x0 0xff8004c0 0x0 0x14>;
88 clocks = <&refclk50mhz>;
92 compatible = "wdt-reboot";
96 uart0: serial@ff800640 {
97 compatible = "brcm,bcm6345-uart";
98 reg = <0x0 0xff800640 0x0 0x18>;
99 clocks = <&periph_osc>;
104 leds: led-controller@ff800800 {
105 compatible = "brcm,bcm6858-leds";
106 reg = <0x0 0xff800800 0x0 0xe4>;
111 gpio0: gpio-controller@0xff800500 {
112 compatible = "brcm,bcm6345-gpio";
113 reg = <0x0 0xff800500 0x0 0x4>,
114 <0x0 0xff800520 0x0 0x4>;
121 gpio1: gpio-controller@0xff800504 {
122 compatible = "brcm,bcm6345-gpio";
123 reg = <0x0 0xff800504 0x0 0x4>,
124 <0x0 0xff800524 0x0 0x4>;
131 gpio2: gpio-controller@0xff800508 {
132 compatible = "brcm,bcm6345-gpio";
133 reg = <0x0 0xff800508 0x0 0x4>,
134 <0x0 0xff800528 0x0 0x4>;
141 gpio3: gpio-controller@0xff80050c {
142 compatible = "brcm,bcm6345-gpio";
143 reg = <0x0 0xff80050c 0x0 0x4>,
144 <0x0 0xff80052c 0x0 0x4>;
151 gpio4: gpio-controller@0xff800510 {
152 compatible = "brcm,bcm6345-gpio";
153 reg = <0x0 0xff800510 0x0 0x4>,
154 <0x0 0xff800530 0x0 0x4>;
161 gpio5: gpio-controller@0xff800514 {
162 compatible = "brcm,bcm6345-gpio";
163 reg = <0x0 0xff800514 0x0 0x4>,
164 <0x0 0xff800534 0x0 0x4>;
171 gpio6: gpio-controller@0xff800518 {
172 compatible = "brcm,bcm6345-gpio";
173 reg = <0x0 0xff800518 0x0 0x4>,
174 <0x0 0xff800538 0x0 0x4>;
181 gpio7: gpio-controller@0xff80051c {
182 compatible = "brcm,bcm6345-gpio";
183 reg = <0x0 0xff80051c 0x0 0x4>,
184 <0x0 0xff80053c 0x0 0x4>;
191 hsspi: spi-controller@ff801000 {
192 compatible = "brcm,bcm6328-hsspi";
193 #address-cells = <1>;
195 reg = <0x0 0xff801000 0x0 0x600>;
196 clocks = <&hsspi_pll>, <&hsspi_pll>;
197 clock-names = "hsspi", "pll";
198 spi-max-frequency = <100000000>;
204 nand: nand-controller@ff801800 {
205 compatible = "brcm,nand-bcm68360",
206 "brcm,brcmnand-v5.0",
208 reg-names = "nand", "nand-int-base", "nand-cache";
209 reg = <0x0 0xff801800 0x0 0x180>,
210 <0x0 0xff802000 0x0 0x10>,
211 <0x0 0xff801c00 0x0 0x200>;
212 parameter-page-big-endian = <0>;