arm64: a37xx: dts: Add pin control nodes to DT
[oweals/u-boot.git] / arch / arm / dts / armada-cp110-slave.dtsi
1 /*
2  * Copyright (C) 2016 Marvell Technology Group Ltd.
3  *
4  * This file is dual-licensed: you can use it either under the terms
5  * of the GPLv2 or the X11 license, at your option. Note that this dual
6  * licensing only applies to this file, and not this project as a
7  * whole.
8  *
9  *  a) This library is free software; you can redistribute it and/or
10  *     modify it under the terms of the GNU General Public License as
11  *     published by the Free Software Foundation; either version 2 of the
12  *     License, or (at your option) any later version.
13  *
14  *     This library is distributed in the hope that it will be useful,
15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  *     GNU General Public License for more details.
18  *
19  * Or, alternatively,
20  *
21  *  b) Permission is hereby granted, free of charge, to any person
22  *     obtaining a copy of this software and associated documentation
23  *     files (the "Software"), to deal in the Software without
24  *     restriction, including without limitation the rights to use,
25  *     copy, modify, merge, publish, distribute, sublicense, and/or
26  *     sell copies of the Software, and to permit persons to whom the
27  *     Software is furnished to do so, subject to the following
28  *     conditions:
29  *
30  *     The above copyright notice and this permission notice shall be
31  *     included in all copies or substantial portions of the Software.
32  *
33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40  *     OTHER DEALINGS IN THE SOFTWARE.
41  */
42
43 /*
44  * Device Tree file for Marvell Armada CP110 Slave.
45  */
46
47 #include <dt-bindings/comphy/comphy_data.h>
48
49 / {
50         cp110-slave {
51                 #address-cells = <2>;
52                 #size-cells = <2>;
53                 compatible = "simple-bus";
54                 interrupt-parent = <&gic>;
55                 ranges;
56
57                 config-space {
58                         #address-cells = <1>;
59                         #size-cells = <1>;
60                         compatible = "simple-bus";
61                         interrupt-parent = <&gic>;
62                         ranges = <0x0 0x0 0xf4000000 0x2000000>;
63
64                         cps_syscon0: system-controller@440000 {
65                                 compatible = "marvell,cp110-system-controller0",
66                                              "syscon";
67                                 reg = <0x440000 0x1000>;
68                                 #clock-cells = <2>;
69                                 core-clock-output-names =
70                                         "cps-apll", "cps-ppv2-core", "cps-eip",
71                                         "cps-core", "cps-nand-core";
72                                 gate-clock-output-names =
73                                         "cps-audio", "cps-communit", "cps-nand",
74                                         "cps-ppv2", "cps-sdio", "cps-mg-domain",
75                                         "cps-mg-core", "cps-xor1", "cps-xor0",
76                                         "cps-gop-dp", "none", "cps-pcie_x10",
77                                         "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
78                                         "cps-sata", "cps-sata-usb", "cps-main",
79                                         "cps-sd-mmc", "none", "none",
80                                         "cps-slow-io", "cps-usb3h0", "cps-usb3h1",
81                                         "cps-usb3dev", "cps-eip150", "cps-eip197";
82                         };
83
84                         cps_pinctl: cps-pinctl@440000 {
85                                 compatible = "marvell,mvebu-pinctrl",
86                                              "marvell,a80x0-cp1-pinctrl";
87                                 bank-name ="cp1-110";
88                                 reg = <0x440000 0x20>;
89                                 pin-count = <63>;
90                                 max-func = <0xf>;
91
92                                 cps_ge1_rgmii_pins: cps-ge-rgmii-pins-0 {
93                                         marvell,pins = < 0  1  2  3  4  5  6  7
94                                                          8  9  10 11 >;
95                                         marvell,function = <3>;
96                                 };
97                                 cps_spi1_pins: cps-spi-pins-1 {
98                                         marvell,pins = < 13 14 15 16 >;
99                                         marvell,function = <3>;
100                                 };
101                         };
102
103                         cps_gpio0: gpio@440100 {
104                                 compatible = "marvell,orion-gpio";
105                                 reg = <0x440100 0x40>;
106                                 ngpios = <32>;
107                                 gpiobase = <20>;
108                                 gpio-controller;
109                                 #gpio-cells = <2>;
110                         };
111
112                         cps_gpio1: gpio@440140 {
113                                 compatible = "marvell,orion-gpio";
114                                 reg = <0x440140 0x40>;
115                                 ngpios = <31>;
116                                 gpiobase = <52>;
117                                 gpio-controller;
118                                 #gpio-cells = <2>;
119                         };
120
121                         cps_sata0: sata@540000 {
122                                 compatible = "marvell,armada-8k-ahci";
123                                 reg = <0x540000 0x30000>;
124                                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
125                                 clocks = <&cps_syscon0 1 15>;
126                                 status = "disabled";
127                         };
128
129                         cps_usb3_0: usb3@500000 {
130                                 compatible = "marvell,armada-8k-xhci",
131                                              "generic-xhci";
132                                 reg = <0x500000 0x4000>;
133                                 dma-coherent;
134                                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
135                                 clocks = <&cps_syscon0 1 22>;
136                                 status = "disabled";
137                         };
138
139                         cps_usb3_1: usb3@510000 {
140                                 compatible = "marvell,armada-8k-xhci",
141                                              "generic-xhci";
142                                 reg = <0x510000 0x4000>;
143                                 dma-coherent;
144                                 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
145                                 clocks = <&cps_syscon0 1 23>;
146                                 status = "disabled";
147                         };
148
149                         cps_xor0: xor@6a0000 {
150                                 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
151                                 reg = <0x6a0000 0x1000>,
152                                       <0x6b0000 0x1000>;
153                                 dma-coherent;
154                                 msi-parent = <&gic_v2m0>;
155                                 clocks = <&cps_syscon0 1 8>;
156                         };
157
158                         cps_xor1: xor@6c0000 {
159                                 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
160                                 reg = <0x6c0000 0x1000>,
161                                       <0x6d0000 0x1000>;
162                                 dma-coherent;
163                                 msi-parent = <&gic_v2m0>;
164                                 clocks = <&cps_syscon0 1 7>;
165                         };
166
167                         cps_spi0: spi@700600 {
168                                 compatible = "marvell,armada-380-spi";
169                                 reg = <0x700600 0x50>;
170                                 #address-cells = <0x1>;
171                                 #size-cells = <0x0>;
172                                 cell-index = <1>;
173                                 clocks = <&cps_syscon0 0 3>;
174                                 status = "disabled";
175                         };
176
177                         cps_spi1: spi@700680 {
178                                 compatible = "marvell,armada-380-spi";
179                                 reg = <0x700680 0x50>;
180                                 #address-cells = <1>;
181                                 #size-cells = <0>;
182                                 cell-index = <2>;
183                                 clocks = <&cps_syscon0 1 21>;
184                                 status = "disabled";
185                         };
186
187                         cps_i2c0: i2c@701000 {
188                                 compatible = "marvell,mv78230-i2c";
189                                 reg = <0x701000 0x20>;
190                                 #address-cells = <1>;
191                                 #size-cells = <0>;
192                                 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
193                                 clocks = <&cps_syscon0 1 21>;
194                                 status = "disabled";
195                         };
196
197                         cps_i2c1: i2c@701100 {
198                                 compatible = "marvell,mv78230-i2c";
199                                 reg = <0x701100 0x20>;
200                                 #address-cells = <1>;
201                                 #size-cells = <0>;
202                                 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
203                                 clocks = <&cps_syscon0 1 21>;
204                                 status = "disabled";
205                         };
206
207                         cps_comphy: comphy@441000 {
208                                 compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
209                                 reg = <0x441000 0x8>,
210                                       <0x120000 0x8>;
211                                 mux-bitcount = <4>;
212                                 max-lanes = <6>;
213                         };
214
215                         cps_utmi0: utmi@580000 {
216                                 compatible = "marvell,mvebu-utmi-2.6.0";
217                                 reg = <0x580000 0x1000>,        /* utmi-unit */
218                                       <0x440420 0x4>,           /* usb-cfg */
219                                       <0x440440 0x4>;           /* utmi-cfg */
220                                 utmi-port = <UTMI_PHY_TO_USB_HOST0>;
221                                 status = "disabled";
222                         };
223                 };
224
225                 cps_pcie0: pcie@f4600000 {
226                         compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
227                         reg = <0 0xf4600000 0 0x10000>,
228                               <0 0xfaf00000 0 0x80000>;
229                         reg-names = "ctrl", "config";
230                         #address-cells = <3>;
231                         #size-cells = <2>;
232                         #interrupt-cells = <1>;
233                         device_type = "pci";
234                         dma-coherent;
235                         msi-parent = <&gic_v2m0>;
236
237                         bus-range = <0 0xff>;
238                         ranges =
239                                 /* downstream I/O */
240                                 <0x81000000 0 0xfd000000 0  0xfd000000 0 0x10000
241                                 /* non-prefetchable memory */
242                                 0x82000000 0 0xfa000000 0  0xfa000000 0 0xf00000>;
243                         interrupt-map-mask = <0 0 0 0>;
244                         interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
245                         interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
246                         num-lanes = <1>;
247                         clocks = <&cps_syscon0 1 13>;
248                         status = "disabled";
249                 };
250
251                 cps_pcie1: pcie@f4620000 {
252                         compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
253                         reg = <0 0xf4620000 0 0x10000>,
254                               <0 0xfbf00000 0 0x80000>;
255                         reg-names = "ctrl", "config";
256                         #address-cells = <3>;
257                         #size-cells = <2>;
258                         #interrupt-cells = <1>;
259                         device_type = "pci";
260                         dma-coherent;
261                         msi-parent = <&gic_v2m0>;
262
263                         bus-range = <0 0xff>;
264                         ranges =
265                                 /* downstream I/O */
266                                 <0x81000000 0 0xfd010000 0  0xfd010000 0 0x10000
267                                 /* non-prefetchable memory */
268                                 0x82000000 0 0xfb000000 0  0xfb000000 0 0xf00000>;
269                         interrupt-map-mask = <0 0 0 0>;
270                         interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
271                         interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
272
273                         num-lanes = <1>;
274                         clocks = <&cps_syscon0 1 11>;
275                         status = "disabled";
276                 };
277
278                 cps_pcie2: pcie@f4640000 {
279                         compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
280                         reg = <0 0xf4640000 0 0x10000>,
281                               <0 0xfcf00000 0 0x80000>;
282                         reg-names = "ctrl", "config";
283                         #address-cells = <3>;
284                         #size-cells = <2>;
285                         #interrupt-cells = <1>;
286                         device_type = "pci";
287                         dma-coherent;
288                         msi-parent = <&gic_v2m0>;
289
290                         bus-range = <0 0xff>;
291                         ranges =
292                                 /* downstream I/O */
293                                 <0x81000000 0 0xfd020000 0  0xfd020000 0 0x10000
294                                 /* non-prefetchable memory */
295                                 0x82000000 0 0xfc000000 0  0xfc000000 0 0xf00000>;
296                         interrupt-map-mask = <0 0 0 0>;
297                         interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
298                         interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
299
300                         num-lanes = <1>;
301                         clocks = <&cps_syscon0 1 12>;
302                         status = "disabled";
303                 };
304         };
305 };