2 * Copyright (C) 2016 Marvell Technology Group Ltd.
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5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
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44 * Device Tree file for Marvell Armada CP110 Slave.
47 #include <dt-bindings/comphy/comphy_data.h>
53 compatible = "simple-bus";
54 interrupt-parent = <&gic>;
60 compatible = "simple-bus";
61 interrupt-parent = <&gic>;
62 ranges = <0x0 0x0 0xf4000000 0x2000000>;
64 cps_ethernet: ethernet@0 {
65 compatible = "marvell,armada-7k-pp22";
66 reg = <0x0 0x100000>, <0x129000 0xb000>;
67 clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
68 clock-names = "pp_clk", "gop_clk", "mg_clk";
73 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
80 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
87 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
94 cps_mdio: mdio@12a200 {
97 compatible = "marvell,orion-mdio";
98 reg = <0x12a200 0x10>;
99 device-name = "cps-mdio";
102 cps_xmdio: mdio@12a600 {
103 #address-cells = <1>;
105 compatible = "marvell,xmdio";
106 reg = <0x12a600 0x16>;
108 device-name = "cps-xmdio";
111 cps_syscon0: system-controller@440000 {
112 compatible = "marvell,cp110-system-controller0",
114 reg = <0x440000 0x1000>;
116 core-clock-output-names =
117 "cps-apll", "cps-ppv2-core", "cps-eip",
118 "cps-core", "cps-nand-core";
119 gate-clock-output-names =
120 "cps-audio", "cps-communit", "cps-nand",
121 "cps-ppv2", "cps-sdio", "cps-mg-domain",
122 "cps-mg-core", "cps-xor1", "cps-xor0",
123 "cps-gop-dp", "none", "cps-pcie_x10",
124 "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
125 "cps-sata", "cps-sata-usb", "cps-main",
126 "cps-sd-mmc", "none", "none",
127 "cps-slow-io", "cps-usb3h0", "cps-usb3h1",
128 "cps-usb3dev", "cps-eip150", "cps-eip197";
131 cps_pinctl: cps-pinctl@440000 {
132 compatible = "marvell,mvebu-pinctrl",
133 "marvell,armada-8k-cps-pinctrl";
134 bank-name ="cp1-110";
135 reg = <0x440000 0x20>;
139 cps_ge1_rgmii_pins: cps-ge-rgmii-pins-0 {
140 marvell,pins = < 0 1 2 3 4 5 6 7
142 marvell,function = <3>;
144 cps_spi1_pins: cps-spi-pins-1 {
145 marvell,pins = < 13 14 15 16 >;
146 marvell,function = <3>;
150 cps_gpio0: gpio@440100 {
151 compatible = "marvell,orion-gpio";
152 reg = <0x440100 0x40>;
159 cps_gpio1: gpio@440140 {
160 compatible = "marvell,orion-gpio";
161 reg = <0x440140 0x40>;
168 cps_sata0: sata@540000 {
169 compatible = "marvell,armada-8k-ahci";
170 reg = <0x540000 0x30000>;
171 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&cps_syscon0 1 15>;
176 cps_usb3_0: usb3@500000 {
177 compatible = "marvell,armada-8k-xhci",
179 reg = <0x500000 0x4000>;
181 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&cps_syscon0 1 22>;
186 cps_usb3_1: usb3@510000 {
187 compatible = "marvell,armada-8k-xhci",
189 reg = <0x510000 0x4000>;
191 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
192 clocks = <&cps_syscon0 1 23>;
196 cps_xor0: xor@6a0000 {
197 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
198 reg = <0x6a0000 0x1000>,
201 msi-parent = <&gic_v2m0>;
202 clocks = <&cps_syscon0 1 8>;
205 cps_xor1: xor@6c0000 {
206 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
207 reg = <0x6c0000 0x1000>,
210 msi-parent = <&gic_v2m0>;
211 clocks = <&cps_syscon0 1 7>;
214 cps_spi0: spi@700600 {
215 compatible = "marvell,armada-380-spi";
216 reg = <0x700600 0x50>;
217 #address-cells = <0x1>;
220 clocks = <&cps_syscon0 0 3>;
224 cps_spi1: spi@700680 {
225 compatible = "marvell,armada-380-spi";
226 reg = <0x700680 0x50>;
227 #address-cells = <1>;
230 clocks = <&cps_syscon0 1 21>;
234 cps_i2c0: i2c@701000 {
235 compatible = "marvell,mv78230-i2c";
236 reg = <0x701000 0x20>;
237 #address-cells = <1>;
239 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&cps_syscon0 1 21>;
244 cps_i2c1: i2c@701100 {
245 compatible = "marvell,mv78230-i2c";
246 reg = <0x701100 0x20>;
247 #address-cells = <1>;
249 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&cps_syscon0 1 21>;
254 cps_comphy: comphy@441000 {
255 compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
256 reg = <0x441000 0x8>,
262 cps_utmi0: utmi@580000 {
263 compatible = "marvell,mvebu-utmi-2.6.0";
264 reg = <0x580000 0x1000>, /* utmi-unit */
265 <0x440420 0x4>, /* usb-cfg */
266 <0x440440 0x4>; /* utmi-cfg */
267 utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
272 cps_pcie0: pcie@f4600000 {
273 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
274 reg = <0 0xf4600000 0 0x10000>,
275 <0 0xfaf00000 0 0x80000>;
276 reg-names = "ctrl", "config";
277 #address-cells = <3>;
279 #interrupt-cells = <1>;
282 msi-parent = <&gic_v2m0>;
284 bus-range = <0 0xff>;
287 <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
288 /* non-prefetchable memory */
289 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
290 interrupt-map-mask = <0 0 0 0>;
291 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
292 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&cps_syscon0 1 13>;
298 cps_pcie1: pcie@f4620000 {
299 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
300 reg = <0 0xf4620000 0 0x10000>,
301 <0 0xfbf00000 0 0x80000>;
302 reg-names = "ctrl", "config";
303 #address-cells = <3>;
305 #interrupt-cells = <1>;
308 msi-parent = <&gic_v2m0>;
310 bus-range = <0 0xff>;
313 <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
314 /* non-prefetchable memory */
315 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
316 interrupt-map-mask = <0 0 0 0>;
317 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
318 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&cps_syscon0 1 11>;
325 cps_pcie2: pcie@f4640000 {
326 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
327 reg = <0 0xf4640000 0 0x10000>,
328 <0 0xfcf00000 0 0x80000>;
329 reg-names = "ctrl", "config";
330 #address-cells = <3>;
332 #interrupt-cells = <1>;
335 msi-parent = <&gic_v2m0>;
337 bus-range = <0 0xff>;
340 <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
341 /* non-prefetchable memory */
342 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
343 interrupt-map-mask = <0 0 0 0>;
344 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
345 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cps_syscon0 1 12>;