1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 SolidRun ltd
6 #include "armada-8040.dtsi"
9 model = "ClearFog-GT-8K";
10 compatible = "solidrun,clearfog-gt-8k",
14 stdout-path = "serial0:115200n8";
24 device_type = "memory";
25 reg = <0x0 0x0 0x0 0x80000000>;
29 compatible = "simple-bus";
31 reg_usb3h0_vbus: usb3-vbus0 {
32 compatible = "regulator-fixed";
33 pinctrl-names = "default";
34 pinctrl-0 = <&cpm_xhci_vbus_pins>;
35 regulator-name = "reg-usb3h0-vbus";
36 regulator-min-microvolt = <5000000>;
37 regulator-max-microvolt = <5000000>;
38 startup-delay-us = <300000>;
39 shutdown-delay-us = <500000>;
40 regulator-force-boot-off;
41 gpio = <&cpm_gpio1 15 GPIO_ACTIVE_LOW>; /* GPIO[47] */
56 /* 0 1 2 3 4 5 6 7 8 9 */
57 pin-func = < 1 1 1 1 1 1 1 1 1 1
58 1 3 0 0 0 0 0 0 0 3 >;
63 pinctrl-names = "default";
64 pinctrl-0 = <&ap_emmc_pins>;
72 * [0-31] = 0xff: Keep default CP0_shared_pins:
73 * [11] CLKOUT_MPP_11 (out)
74 * [23] LINK_RD_IN_CP2CP (in)
75 * [25] CLKOUT_MPP_25 (out)
76 * [29] AVS_FB_IN_CP2CP (in)
77 * [32, 33, 34] pci0/1/2 reset
78 * [35-38] CP0 I2C1 and I2C0
79 * [39] GPIO reset button
80 * [40,41] LED0 and LED1
82 * [47] USB VBUS EN (active low)
84 * [49] SFP+ present signal
90 * [55] Micro SD card detect
93 /* 0 1 2 3 4 5 6 7 8 9 */
94 pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
95 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
96 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
97 0xff 0 0 0 0 2 2 2 2 0
99 0 0 0 0 0 0 0xe 0xe 0xe 0xe
102 cpm_pcie_reset_pins: cpm-pcie-reset-pins {
103 marvell,pins = < 32 >;
104 marvell,function = <0>;
107 cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
108 marvell,pins = < 47 >;
109 marvell,function = <0>;
112 cps_1g_phy_reset: cps-1g-phy-reset {
113 marvell,pins = < 43 >;
114 marvell,function = <0>;
120 pinctrl-names = "default";
121 pinctrl-0 = <&cpm_sdhci_pins>;
128 pinctrl-names = "default";
129 pinctrl-0 = <&cpm_pcie_reset_pins>;
130 marvell,reset-gpio = <&cpm_gpio1 0 GPIO_ACTIVE_LOW>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&cpm_i2c0_pins>;
138 clock-frequency = <100000>;
142 pinctrl-names = "default";
143 pinctrl-0 = <&cpm_i2c1_pins>;
145 clock-frequency = <100000>;
154 * CP0 Serdes Configuration:
156 * Lane 1: Not connected
158 * Lane 3: Not connected
159 * Lane 4: USB 3.0 host port1 (can be PCIe)
160 * Lane 5: Not connected
163 phy-type = <PHY_TYPE_PEX0>;
166 phy-type = <PHY_TYPE_UNCONNECTED>;
169 phy-type = <PHY_TYPE_SFI>;
172 phy-type = <PHY_TYPE_UNCONNECTED>;
175 phy-type = <PHY_TYPE_USB3_HOST1>;
178 phy-type = <PHY_TYPE_UNCONNECTED>;
183 pinctrl-names = "default";
198 vbus-supply = <®_usb3h0_vbus>;
211 * [7] CP1 SPI0 CSn1 (FXS)
212 * [8] CP1 SPI0 CSn0 (TPM)
213 * [9.11]CP1 SPI0 MOSI/MISO/CLK
214 * [13] CP1 SPI1 MISO (TDM and SPI ROM shared)
215 * [14] CP1 SPI1 CS0n (64Mb SPI ROM)
216 * [15] CP1 SPI1 MOSI (TDM and SPI ROM shared)
217 * [16] CP1 SPI1 CLK (TDM and SPI ROM shared)
218 * [24] Topaz switch reset
222 * [29] CP0 10G SFP TX Disable
224 * [31] Front panel button
225 * [32-62] = 0xff: Keep default CP1_shared_pins:
227 /* 0 1 2 3 4 5 6 7 8 9 */
228 pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x0 0x4 0x4 0x4
229 0x4 0x4 0x0 0x3 0x3 0x3 0x3 0xff 0xff 0xff
230 0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x8 0x8 0x0
231 0x0 0x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff
232 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
233 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
238 pinctrl-names = "default";
239 pinctrl-0 = <&cps_spi1_pins>;
243 compatible = "jedec,spi-nor";
245 spi-max-frequency = <10000000>;
248 compatible = "fixed-partitions";
249 #address-cells = <1>;
257 label = "Filesystem";
258 reg = <0x200000 0xce0000>;
266 * CP1 Serdes Configuration:
267 * Lane 0: SATA 1 (RX swapped). Can be PCIe0
270 * Lane 3: SGMII1 - Connected to 1512 port
272 * Lane 5: SGMII2 - Connected to Topaz switch
275 phy-type = <PHY_TYPE_SATA1>;
276 phy-invert = <PHY_POLARITY_RXD_INVERT>;
279 phy-type = <PHY_TYPE_UNCONNECTED>;
282 phy-type = <PHY_TYPE_USB3_HOST0>;
285 phy-type = <PHY_TYPE_SGMII1>;
286 phy-speed = <PHY_SPEED_1_25G>;
289 phy-type = <PHY_TYPE_UNCONNECTED>;
292 phy-type = <PHY_TYPE_SGMII2>;
293 phy-speed = <PHY_SPEED_3_125G>;
298 phy0: ethernet-phy@0 {
304 pinctrl-names = "default";
305 pinctrl-0 = <&cps_1g_phy_reset>;
314 phy-reset-gpios = <&cpm_gpio1 11 GPIO_ACTIVE_LOW>;
317 /* 2.5G to Topaz switch */
322 phy-reset-gpios = <&cps_gpio0 24 GPIO_ACTIVE_LOW>;