arch/arm/dts/armada-8040-clearfog-gt-8k.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 SolidRun ltd
   4  */
   5
   6 #include "armada-8040.dtsi"
   7
   8 / {
   9         model = "ClearFog-GT-8K";
  10         compatible = "solidrun,clearfog-gt-8k",
  11                      "marvell,armada8040";
  12
  13         chosen {
  14                 stdout-path = "serial0:115200n8";
  15         };
  16
  17         aliases {
  18                 i2c0 = &cpm_i2c0;
  19                 i2c1 = &cpm_i2c1;
  20                 spi0 = &cps_spi1;
  21         };
  22
  23         memory@00000000 {
  24                 device_type = "memory";
  25                 reg = <0x0 0x0 0x0 0x80000000>;
  26         };
  27
  28         simple-bus {
  29                 compatible = "simple-bus";
  30
  31                 reg_usb3h0_vbus: usb3-vbus0 {
  32                         compatible = "regulator-fixed";
  33                         pinctrl-names = "default";
  34                         pinctrl-0 = <&cpm_xhci_vbus_pins>;
  35                         regulator-name = "reg-usb3h0-vbus";
  36                         regulator-min-microvolt = <5000000>;
  37                         regulator-max-microvolt = <5000000>;
  38                         startup-delay-us = <300000>;
  39                         shutdown-delay-us = <500000>;
  40                         regulator-force-boot-off;
  41                         gpio = <&cpm_gpio1 15 GPIO_ACTIVE_LOW>; /* GPIO[47] */
  42                 };
  43         };
  44 };
  45
  46 &uart0 {
  47         status = "okay";
  48 };
  49
  50 &ap_pinctl {
  51         /*
  52          * MPP Bus:
  53          * eMMC [0-10]
  54          * UART0 [11,19]
  55          */
  56                   /* 0 1 2 3 4 5 6 7 8 9 */
  57         pin-func = < 1 1 1 1 1 1 1 1 1 1
  58                      1 3 0 0 0 0 0 0 0 3 >;
  59 };
  60
  61 /* on-board eMMC */
  62 &ap_sdhci0 {
  63         pinctrl-names = "default";
  64         pinctrl-0 = <&ap_emmc_pins>;
  65         bus-width = <8>;
  66         status = "okay";
  67 };
  68
  69 &cpm_pinctl {
  70         /*
  71          * MPP Bus:
  72          * [0-31] = 0xff: Keep default CP0_shared_pins:
  73          * [11] CLKOUT_MPP_11 (out)
  74          * [23] LINK_RD_IN_CP2CP (in)
  75          * [25] CLKOUT_MPP_25 (out)
  76          * [29] AVS_FB_IN_CP2CP (in)
  77          * [32, 33, 34] pci0/1/2 reset
  78          * [35-38] CP0 I2C1 and I2C0
  79          * [39] GPIO reset button
  80          * [40,41] LED0 and LED1
  81          * [43] 1512 phy reset
  82          * [47] USB VBUS EN (active low)
  83          * [48] FAN PWM
  84          * [49] SFP+ present signal
  85          * [50] TPM interrupt
  86          * [51] WLAN0 disable
  87          * [52] WLAN1 disable
  88          * [53] LTE disable
  89          * [54] NFC reset
  90          * [55] Micro SD card detect
  91          * [56-61] Micro SD
  92          */
  93                 /*   0    1    2    3    4    5    6    7    8    9 */
  94         pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
  95                      0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
  96                      0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
  97                      0xff 0    0    0    0    2    2    2    2    0
  98                      0    0    0    0    0    0    0    0    0    0
  99                      0    0    0    0    0    0    0xe  0xe  0xe  0xe
 100                      0xe  0xe  0 >;
 101
 102         cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
 103                 marvell,pins = < 47 >;
 104                 marvell,function = <0>;
 105         };
 106
 107         cps_1g_phy_reset: cps-1g-phy-reset {
 108                 marvell,pins = < 43 >;
 109                 marvell,function = <0>;
 110         };
 111 };
 112
 113 /* uSD slot */
 114 &cpm_sdhci0 {
 115         pinctrl-names = "default";
 116         pinctrl-0 = <&cpm_sdhci_pins>;
 117         bus-width = <4>;
 118         status = "okay";
 119 };
 120
 121 &cpm_pcie0 {
 122         num-lanes = <1>;
 123         status = "okay";
 124 };
 125
 126 &cpm_i2c0 {
 127         pinctrl-names = "default";
 128         pinctrl-0 = <&cpm_i2c0_pins>;
 129         status = "okay";
 130         clock-frequency = <100000>;
 131 };
 132
 133 &cpm_i2c1 {
 134         pinctrl-names = "default";
 135         pinctrl-0 = <&cpm_i2c1_pins>;
 136         status = "okay";
 137         clock-frequency = <100000>;
 138 };
 139
 140 &cpm_sata0 {
 141         status = "okay";
 142 };
 143
 144 &cpm_comphy {
 145         /*
 146          * CP0 Serdes Configuration:
 147          * Lane 0: PCIe0 (x1)
 148          * Lane 1: Not connected
 149          * Lane 2: SFI (10G)
 150          * Lane 3: Not connected
 151          * Lane 4: USB 3.0 host port1 (can be PCIe)
 152          * Lane 5: Not connected
 153          */
 154         phy0 {
 155                 phy-type = <PHY_TYPE_PEX0>;
 156         };
 157         phy1 {
 158                 phy-type = <PHY_TYPE_UNCONNECTED>;
 159         };
 160         phy2 {
 161                 phy-type = <PHY_TYPE_SFI>;
 162         };
 163         phy3 {
 164                 phy-type = <PHY_TYPE_UNCONNECTED>;
 165         };
 166         phy4 {
 167                 phy-type = <PHY_TYPE_USB3_HOST1>;
 168         };
 169         phy5 {
 170                 phy-type = <PHY_TYPE_UNCONNECTED>;
 171         };
 172 };
 173
 174 &cpm_ethernet {
 175         pinctrl-names = "default";
 176         status = "okay";
 177 };
 178
 179 /* 10G SFI SFP */
 180 &cpm_eth0 {
 181         status = "okay";
 182         phy-mode = "sfi";
 183 };
 184
 185 &cps_sata0 {
 186         status = "okay";
 187 };
 188
 189 &cps_usb3_0 {
 190         vbus-supply = <&reg_usb3h0_vbus>;
 191         status = "okay";
 192 };
 193
 194 &cps_utmi0 {
 195         status = "okay";
 196 };
 197
 198 &cps_pinctl {
 199         /*
 200          * MPP Bus:
 201          * [0-5] TDM
 202          * [6]   VHV Enable
 203          * [7]   CP1 SPI0 CSn1 (FXS)
 204          * [8]   CP1 SPI0 CSn0 (TPM)
 205          * [9.11]CP1 SPI0 MOSI/MISO/CLK
 206          * [13]  CP1 SPI1 MISO (TDM and SPI ROM shared)
 207          * [14]  CP1 SPI1 CS0n (64Mb SPI ROM)
 208          * [15]  CP1 SPI1 MOSI (TDM and SPI ROM shared)
 209          * [16]  CP1 SPI1 CLK (TDM and SPI ROM shared)
 210          * [24]  Topaz switch reset
 211          * [26]  Buzzer
 212          * [27]  CP1 SMI MDIO
 213          * [28]  CP1 SMI MDC
 214          * [29]  CP0 10G SFP TX Disable
 215          * [30]  WPS button
 216          * [31]  Front panel button
 217          * [32-62] = 0xff: Keep default CP1_shared_pins:
 218          */
 219                 /*   0    1    2    3    4    5    6    7    8    9 */
 220         pin-func = < 0x4  0x4  0x4  0x4  0x4  0x4  0x0  0x4  0x4  0x4
 221                      0x4  0x4  0x0  0x3  0x3  0x3  0x3  0xff 0xff 0xff
 222                      0xff 0xff 0xff 0xff 0x0  0xff 0x0  0x8  0x8  0x0
 223                      0x0  0x0  0x0  0xff 0xff 0xff 0xff 0xff 0xff 0xff
 224                      0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 225                      0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 226                      0xff 0xff 0xff>;
 227 };
 228
 229 &cps_spi1 {
 230         pinctrl-names = "default";
 231         pinctrl-0 = <&cps_spi1_pins>;
 232         status = "okay";
 233
 234         spi-flash@0 {
 235                 compatible = "jedec,spi-nor", "spi-flash";
 236                 reg = <0>;
 237                 spi-max-frequency = <10000000>;
 238
 239                 partitions {
 240                         compatible = "fixed-partitions";
 241                         #address-cells = <1>;
 242                         #size-cells = <1>;
 243
 244                         partition@0 {
 245                                 label = "U-Boot";
 246                                 reg = <0 0x200000>;
 247                         };
 248                         partition@200000 {
 249                                 label = "Filesystem";
 250                                 reg = <0x200000 0xce0000>;
 251                         };
 252                 };
 253         };
 254 };
 255
 256 &cps_comphy {
 257         /*
 258          * CP1 Serdes Configuration:
 259          * Lane 0: SATA 1 (RX swapped). Can be PCIe0
 260          * Lane 1: Not used
 261          * Lane 2: USB HOST 0
 262          * Lane 3: SGMII1 - Connected to 1512 port
 263          * Lane 4: Not used
 264          * Lane 5: SGMII2 - Connected to Topaz switch
 265          */
 266         phy0 {
 267                 phy-type = <PHY_TYPE_SATA1>;
 268                 phy-invert = <PHY_POLARITY_RXD_INVERT>;
 269         };
 270         phy1 {
 271                 phy-type = <PHY_TYPE_UNCONNECTED>;
 272         };
 273         phy2 {
 274                 phy-type = <PHY_TYPE_USB3_HOST0>;
 275         };
 276         phy3 {
 277                 phy-type = <PHY_TYPE_SGMII1>;
 278                 phy-speed = <PHY_SPEED_1_25G>;
 279         };
 280         phy4 {
 281                 phy-type = <PHY_TYPE_UNCONNECTED>;
 282         };
 283         phy5 {
 284                 phy-type = <PHY_TYPE_SGMII2>;
 285                 phy-speed = <PHY_SPEED_3_125G>;
 286         };
 287 };
 288
 289 &cps_mdio {
 290         phy0: ethernet-phy@0 {
 291                 reg = <0>;
 292         };
 293 };
 294
 295 &cps_ethernet {
 296         pinctrl-names = "default";
 297         pinctrl-0 = <&cps_1g_phy_reset>;
 298         status = "okay";
 299 };
 300
 301 /* 1G SGMII */
 302 &cps_eth1 {
 303         status = "okay";
 304         phy-mode = "sgmii";
 305         phy = <&phy0>;
 306         phy-reset-gpios = <&cpm_gpio1 11 GPIO_ACTIVE_LOW>;
 307 };
 308
 309 /* 2.5G to Topaz switch */
 310 &cps_eth2 {
 311         status = "okay";
 312         phy-mode = "sgmii";
 313         phy-speed = <2500>;
 314         phy-reset-gpios = <&cps_gpio0 24 GPIO_ACTIVE_LOW>;
 315 };