2 * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
4 * Copyright (C) 2015 Russell King
6 * This board is in development; the contents of this file work with
7 * the A1 rev 2.0 of the board, which does not represent final
8 * production board. Things will change, don't expect this file to
9 * remain compatible info the future.
11 * This file is dual-licensed: you can use it either under the terms
12 * of the GPL or the X11 license, at your option. Note that this dual
13 * licensing only applies to this file, and not this project as a
16 * a) This file is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License
18 * version 2 as published by the Free Software Foundation.
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
50 #include <dt-bindings/input/input.h>
51 #include <dt-bindings/gpio/gpio.h>
52 #include "armada-388.dtsi"
53 #include "armada-38x-solidrun-microsom.dtsi"
56 model = "SolidRun Clearfog A1";
57 compatible = "solidrun,clearfog-a1", "marvell,armada388",
58 "marvell,armada385", "marvell,armada380";
61 /* So that mvebu u-boot can update the MAC addresses */
71 stdout-path = "serial0:115200n8";
74 reg_3p3v: regulator-3p3v {
75 compatible = "regulator-fixed";
76 regulator-name = "3P3V";
77 regulator-min-microvolt = <3300000>;
78 regulator-max-microvolt = <3300000>;
86 * If the rtc doesn't work, run "date reset"
104 cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
106 pinctrl-0 = <µsom_sdhci_pins
107 &clearfog_sdhci_cd_pins>;
108 pinctrl-names = "default";
116 pinctrl-0 = <&mikro_uart_pins>;
117 pinctrl-names = "default";
122 /* CON7, USB-A port on back of device */
130 * The two PCIe units are accessible through
131 * the mini-PCIe connectors on the board.
134 /* Port 1, Lane 0. CONN3, nearest power. */
135 reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
139 /* Port 2, Lane 0. CONN2, nearest CPU. */
140 reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
147 compatible = "gpio-keys";
148 pinctrl-0 = <&rear_button_pins>;
149 pinctrl-names = "default";
152 /* The rear SW3 button */
153 label = "Rear Button";
154 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
156 linux,code = <BTN_0>;
166 managed = "in-band-status";
177 clock-frequency = <400000>;
178 pinctrl-0 = <&i2c0_pins>;
179 pinctrl-names = "default";
183 * PCA9655 GPIO expander, up to 1MHz clock.
201 expander0: gpio-expander@20 {
203 * This is how it should be:
204 * compatible = "onnn,pca9655",
206 * but you can't do this because of
209 compatible = "nxp,pca9555";
216 gpios = <0 GPIO_ACTIVE_LOW>;
218 line-name = "pcie1.0-clkreq";
222 gpios = <3 GPIO_ACTIVE_LOW>;
224 line-name = "pcie1.0-w-disable";
228 gpios = <4 GPIO_ACTIVE_LOW>;
230 line-name = "pcie2.0-clkreq";
234 gpios = <7 GPIO_ACTIVE_LOW>;
236 line-name = "pcie2.0-w-disable";
240 gpios = <5 GPIO_ACTIVE_LOW>;
242 line-name = "usb3-current-limit";
246 gpios = <6 GPIO_ACTIVE_HIGH>;
248 line-name = "usb3-power";
252 gpios = <11 GPIO_ACTIVE_HIGH>;
254 line-name = "m.2 devslp";
258 mikrobus_adc: mcp3021@4c {
259 compatible = "microchip,mcp3021";
266 * Routed to SFP, mikrobus, and PCIe.
267 * SFP limits this to 100kHz, and requires
268 * an AT24C01A/02/04 with address pins tied
269 * low, which takes addresses 0x50 and 0x51.
270 * Mikrobus doesn't specify beyond an I2C
272 * PCIe uses ARP to assign addresses, or
275 clock-frequency = <100000>;
276 pinctrl-0 = <&clearfog_i2c1_pins>;
277 pinctrl-names = "default";
282 clearfog_i2c1_pins: i2c1-pins {
283 /* SFP, PCIe, mSATA, mikrobus */
284 marvell,pins = "mpp26", "mpp27";
285 marvell,function = "i2c1";
287 clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
288 marvell,pins = "mpp20";
289 marvell,function = "gpio";
291 clearfog_spi1_cs_pins: spi1-cs-pins {
292 marvell,pins = "mpp55";
293 marvell,function = "spi1";
295 mikro_pins: mikro-pins {
296 /* int: mpp22 rst: mpp29 */
297 marvell,pins = "mpp22", "mpp29";
298 marvell,function = "gpio";
300 mikro_spi_pins: mikro-spi-pins {
301 marvell,pins = "mpp43";
302 marvell,function = "spi1";
304 mikro_uart_pins: mikro-uart-pins {
305 marvell,pins = "mpp24", "mpp25";
306 marvell,function = "ua1";
308 rear_button_pins: rear-button-pins {
309 marvell,pins = "mpp34";
310 marvell,function = "gpio";
316 * Add SPI CS pins for clearfog:
321 pinctrl-0 = <&spi1_pins &mikro_spi_pins>;
322 pinctrl-names = "default";
327 +#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
328 MPP18: gpio ? (pca9655 int?)
329 MPP19: gpio ? (clkreq?)
330 MPP20: gpio ? (sd0 detect)
332 MPP22: gpio x mikro int
333 MPP23: gpio x switch irq
334 +#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333
335 MPP24: ua1:rxd x mikro rx
336 MPP25: ua1:txd x mikro tx
337 MPP26: i2c1:sck x mikro sck
338 MPP27: i2c1:sda x mikro sda
340 MPP29: gpio x mikro rst
341 MPP30: ge1:txd2 ? (config)
342 MPP31: ge1:txd3 ? (config)
343 +#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002
344 MPP32: ge1:txctl ? (unused)
345 MPP33: gpio ? (pic_com0)
346 MPP34: gpio x rear button (pic_com1)
347 MPP35: gpio ? (pic_com2)
348 MPP36: gpio ? (unused)
352 +#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004
354 MPP41: gpio x switch reset
356 MPP43: spi1:cs2 x mikro cs
357 MPP44: sata3:prsnt ? (unused)
358 MPP45: ref:clk_out0 ?
359 MPP46: ref:clk_out1 x switch clk
361 +#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333
369 MPP55: spi1:cs1 x slic
370 +#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444
371 MPP56: spi1:mosi x mikro mosi
372 MPP57: spi1:sck x mikro sck
373 MPP58: spi1:miso x mikro miso
374 MPP59: spi1:cs0 x w25q32