arch/arm/dts/armada-385-atl-x530.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include "armada-385.dtsi"
   5
   6 / {
   7         model = "Allied Telesis x530";
   8         compatible = "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
   9
  10         chosen {
  11                 stdout-path = "serial0:115200n8";
  12                 bootargs = "console=ttyS0,115200 earlyprintk";
  13         };
  14
  15         aliases {
  16                 spi1 = &spi1;
  17                 i2c0 = &i2c0;
  18         };
  19
  20         memory {
  21                 device_type = "memory";
  22                 reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
  23         };
  24
  25         soc {
  26                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  27                           MBUS_ID(0x01, 0x3d) 0 0xf4800000 0x80000
  28                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
  29
  30                 pcie-mem-aperture = <0xa0000000 0x40000000>;
  31         };
  32
  33         eco-button-interrupt {
  34                 compatible = "atl,eco-button-interrupt";
  35                 eco-button-gpio = <&gpio0 14 GPIO_ACTIVE_LOW>;
  36         };
  37
  38         board-reset {
  39                 compatible = "atl,phy_reset";
  40                 /* Physical board layout of reset pin is active-low but for the
  41                  * current driver we have to set it to active-high here.
  42                  */
  43                 phy-reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
  44                                  <&gpio1 21 GPIO_ACTIVE_HIGH>;
  45         };
  46
  47         phy-int {
  48                 compatible = "linux,uio-pdrv-genirq";
  49                 interrupt-parent = <&gpio0>;
  50                 interrupts = <6 IRQ_TYPE_EDGE_BOTH>;
  51         };
  52
  53         led-enable {
  54                 compatible = "atl,led-enable";
  55                 led-enable-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
  56         };
  57
  58         led_7seg {
  59                 compatible = "atl,of-led-7seg";
  60                 segment-gpios = <
  61                         &led_7seg_gpio 0 0
  62                         &led_7seg_gpio 1 0
  63                         &led_7seg_gpio 2 0
  64                         &led_7seg_gpio 3 0
  65                         &led_7seg_gpio 4 0
  66                         &led_7seg_gpio 5 0
  67                         &led_7seg_gpio 6 0
  68                         &led_7seg_gpio 7 0>;
  69         };
  70
  71         poe {
  72                 compatible = "atl,periph-poe";
  73                 poe-reset-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
  74                 interrupt-parent = <&gpio0>;
  75                 interrupts = <20 IRQ_TYPE_EDGE_BOTH>;
  76         };
  77 };
  78
  79 &pciec {
  80         status = "okay";
  81 };
  82
  83 &pcie1 {
  84         status = "okay";
  85 };
  86
  87 &devbus_cs1 {
  88         compatible = "marvell,mvebu-devbus";
  89         status = "okay";
  90
  91         devbus,bus-width    = <8>;
  92         devbus,turn-off-ps  = <60000>;
  93         devbus,badr-skew-ps = <0>;
  94         devbus,acc-first-ps = <124000>;
  95         devbus,acc-next-ps  = <248000>;
  96         devbus,rd-setup-ps  = <0>;
  97         devbus,rd-hold-ps   = <0>;
  98
  99         /* Write parameters */
 100         devbus,sync-enable = <0>;
 101         devbus,wr-high-ps  = <60000>;
 102         devbus,wr-low-ps   = <60000>;
 103         devbus,ale-wr-ps   = <60000>;
 104
 105         nvs@0 {
 106                 status = "okay";
 107
 108                 compatible = "mtd-ram";
 109                 reg = <0 0x00080000>;
 110                 bank-width = <1>;
 111                 label = "nvs";
 112         };
 113 };
 114
 115 &gpio0 {
 116         poe-disable {
 117                 gpio-hog;
 118                 gpios = <16 GPIO_ACTIVE_HIGH>;
 119                 output-high;
 120                 line-name = "poe-disable";
 121         };
 122 };
 123
 124 &gpio1 {
 125         poe-mezz-reset {
 126                 gpio-hog;
 127                 gpios = <15 GPIO_ACTIVE_HIGH>;
 128                 output-high;
 129                 line-name = "poe-mezz-reset";
 130         };
 131 };
 132
 133 &i2c0 {
 134         clock-frequency = <100000>;
 135         status = "okay";
 136
 137         mux@71 {
 138                 #address-cells = <1>;
 139                 #size-cells = <0>;
 140                 compatible = "nxp,pca9544";
 141                 reg = <0x71>;
 142                 i2c-mux-idle-disconnect;
 143
 144                 i2c@0 { /* POE devices MUX */
 145                         #address-cells = <1>;
 146                         #size-cells = <0>;
 147                         reg = <0>;
 148                 };
 149
 150                 i2c@1 {
 151                         #address-cells = <1>;
 152                         #size-cells = <0>;
 153                         reg = <1>;
 154
 155                         rng@3b {
 156                                 compatible = "maxim,ds2476";
 157                                 reg = <0x3b>;
 158                         };
 159
 160                         hwmon@2e {
 161                                 compatible = "adi,adt7476";
 162                                 reg = <0x2e>;
 163                         };
 164
 165                         hwmon@2d {
 166                                 compatible = "adi,adt7476";
 167                                 reg = <0x2d>;
 168                         };
 169
 170                 };
 171
 172                 i2c@2 {
 173                         #address-cells = <1>;
 174                         #size-cells = <0>;
 175                         reg = <2>;
 176
 177                         rtc@68 {
 178                                 compatible = "dallas,ds1340";
 179                                 reg = <0x68>;
 180                         };
 181                 };
 182
 183                 i2c@3 {
 184                         #address-cells = <1>;
 185                         #size-cells = <0>;
 186                         reg = <3>;
 187
 188                         led_7seg_gpio: gpio@20 {
 189                                 compatible = "nxp,pca9554";
 190                                 gpio-controller;
 191                                 #gpio-cells = <2>;
 192                                 reg = <0x20>;
 193                         };
 194
 195                         sfpgpio: gpio@27 { /* I2C to GPIO */
 196                                 compatible = "nxp,pca9555";
 197                                 gpio-controller;
 198                                 #gpio-cells = <2>;
 199                                 reg = <0x27>;
 200                                 interrupt-parent = <&gpio0>;
 201                                 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
 202                         };
 203
 204                         sfpmux: mux@77 { /* SFP I2C MUX */
 205                                 #address-cells = <1>;
 206                                 #size-cells = <0>;
 207                                 compatible = "nxp,pca9544";
 208                                 reg = <0x77>;
 209                                 i2c-mux-idle-disconnect;
 210                         };
 211                 };
 212         };
 213 };
 214
 215 &spi1 {
 216         status = "okay";
 217
 218         spi-flash@0 {
 219                 #address-cells = <1>;
 220                 #size-cells = <1>;
 221                 compatible = "jedec,spi-nor";
 222                 reg = <0>; /* Chip select 0 */
 223                 spi-max-frequency = <50000000>;
 224                 m25p,fast-read;
 225
 226                 partition@u-boot {
 227                         reg = <0x00000000 0x00100000>;
 228                         label = "u-boot";
 229                 };
 230                 partition@u-boot-env {
 231                         reg = <0x00100000 0x00040000>;
 232                         label = "u-boot-env";
 233                 };
 234                 partition@unused {
 235                         reg = <0x00140000 0x00e80000>;
 236                         label = "unused";
 237                 };
 238                 partition@idprom {
 239                         reg = <0x00fc0000 0x00040000>;
 240                         label = "idprom";
 241                 };
 242         };
 243 };
 244
 245 &uart0 {
 246         pinctrl-names = "default";
 247         pinctrl-0 = <&uart0_pins>;
 248         status = "okay";
 249 };
 250
 251 &usb0 {
 252         status = "okay";
 253 };
 254
 255 &refclk {
 256         clock-frequency = <25000000>;
 257 };
 258
 259 &nand_controller { /* 256 MB */
 260         status = "okay";
 261         num-cs = <1>;
 262         nand-ecc-strength = <4>;
 263         nand-ecc-step-size = <512>;
 264         marvell,nand-enable-arbiter;
 265         nand-on-flash-bbt;
 266 };