1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
5 * Copyright (C) 2012 Marvell
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * Ben Dooks <ben.dooks@codethink.co.uk>
12 * This file contains the definitions that are common to the Armada
13 * 370 and Armada XP SoC.
16 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
19 model = "Marvell Armada 370 and XP SoC";
20 compatible = "marvell,armada-370-xp";
31 compatible = "marvell,sheeva-v7";
38 compatible = "arm,cortex-a9-pmu";
39 interrupts-extended = <&mpic 3>;
45 controller = <&mbusc>;
46 interrupt-parent = <&mpic>;
47 pcie-mem-aperture = <0xf8000000 0x7e00000>;
48 pcie-io-aperture = <0xffe00000 0x100000>;
50 devbus_bootcs: devbus-bootcs {
51 compatible = "marvell,mvebu-devbus";
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
60 devbus_cs0: devbus-cs0 {
61 compatible = "marvell,mvebu-devbus";
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
66 clocks = <&coreclk 0>;
70 devbus_cs1: devbus-cs1 {
71 compatible = "marvell,mvebu-devbus";
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
73 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
76 clocks = <&coreclk 0>;
80 devbus_cs2: devbus-cs2 {
81 compatible = "marvell,mvebu-devbus";
82 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
83 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
86 clocks = <&coreclk 0>;
90 devbus_cs3: devbus-cs3 {
91 compatible = "marvell,mvebu-devbus";
92 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
93 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
96 clocks = <&coreclk 0>;
101 compatible = "simple-bus";
102 #address-cells = <1>;
104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
108 compatible = "marvell,orion-rtc";
109 reg = <0x10300 0x20>;
114 compatible = "marvell,mv64xxx-i2c";
115 #address-cells = <1>;
119 clocks = <&coreclk 0>;
124 compatible = "marvell,mv64xxx-i2c";
125 #address-cells = <1>;
129 clocks = <&coreclk 0>;
133 uart0: serial@12000 {
134 compatible = "snps,dw-apb-uart";
135 reg = <0x12000 0x100>;
139 clocks = <&coreclk 0>;
143 uart1: serial@12100 {
144 compatible = "snps,dw-apb-uart";
145 reg = <0x12100 0x100>;
149 clocks = <&coreclk 0>;
153 pinctrl: pin-ctrl@18000 {
154 reg = <0x18000 0x38>;
157 coredivclk: corediv-clock@18740 {
158 compatible = "marvell,armada-370-corediv-clock";
162 clock-output-names = "nand";
165 mbusc: mbus-controller@20000 {
166 compatible = "marvell,mbus-controller";
167 reg = <0x20000 0x100>, <0x20180 0x20>,
171 mpic: interrupt-controller@20a00 {
172 compatible = "marvell,mpic";
173 #interrupt-cells = <1>;
175 interrupt-controller;
179 coherencyfab: coherency-fabric@20200 {
180 compatible = "marvell,coherency-fabric";
181 reg = <0x20200 0xb0>, <0x21010 0x1c>;
185 reg = <0x20300 0x30>, <0x21040 0x30>;
186 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
189 watchdog: watchdog@20300 {
190 reg = <0x20300 0x34>, <0x20704 0x4>;
193 cpurst: cpurst@20800 {
194 compatible = "marvell,armada-370-cpu-reset";
199 compatible = "marvell,armada-370-pmsu";
200 reg = <0x22000 0x1000>;
204 compatible = "marvell,orion-ehci";
205 reg = <0x50000 0x500>;
211 compatible = "marvell,orion-ehci";
212 reg = <0x51000 0x500>;
217 eth0: ethernet@70000 {
218 reg = <0x70000 0x4000>;
220 clocks = <&gateclk 4>;
225 #address-cells = <1>;
227 compatible = "marvell,orion-mdio";
229 clocks = <&gateclk 4>;
232 eth1: ethernet@74000 {
233 reg = <0x74000 0x4000>;
235 clocks = <&gateclk 3>;
240 compatible = "marvell,armada-370-sata";
241 reg = <0xa0000 0x5000>;
243 clocks = <&gateclk 15>, <&gateclk 30>;
244 clock-names = "0", "1";
249 compatible = "marvell,armada370-nand";
250 reg = <0xd0000 0x54>;
251 #address-cells = <1>;
254 clocks = <&coredivclk 0>;
259 compatible = "marvell,orion-sdio";
260 reg = <0xd4000 0x200>;
262 clocks = <&gateclk 17>;
272 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
273 <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
274 <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
275 <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
276 <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
277 <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
278 <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
279 <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
280 <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
281 #address-cells = <1>;
285 clocks = <&coreclk 0>;
290 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x28>, /* control */
291 <MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */
292 <MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
293 <MBUS_ID(0x01, 0x9a) 0 0xffffffff>, /* CS2 */
294 <MBUS_ID(0x01, 0xda) 0 0xffffffff>, /* CS3 */
295 <MBUS_ID(0x01, 0x1b) 0 0xffffffff>, /* CS4 */
296 <MBUS_ID(0x01, 0x5b) 0 0xffffffff>, /* CS5 */
297 <MBUS_ID(0x01, 0x9b) 0 0xffffffff>, /* CS6 */
298 <MBUS_ID(0x01, 0xdb) 0 0xffffffff>; /* CS7 */
299 #address-cells = <1>;
303 clocks = <&coreclk 0>;
309 /* 2 GHz fixed main PLL */
311 compatible = "fixed-clock";
313 clock-frequency = <2000000000>;