1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Phytec Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 model = "Phytec AM335x phyBOARD-WEGA";
13 compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx";
16 compatible = "ti,da830-evm-audio";
20 compatible = "simple-bus";
22 vcc3v3: fixedregulator1 {
23 compatible = "regulator-fixed";
24 regulator-name = "vcc3v3";
25 regulator-min-microvolt = <3300000>;
26 regulator-max-microvolt = <3300000>;
34 mcasp0_pins: pinmux_mcasp0 {
35 pinctrl-single,pins = <
36 AM33XX_IOPAD(0x9AC, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahclkx.mcasp0_ahclkx */
37 AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */
38 AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */
39 AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */
40 AM33XX_IOPAD(0x9A8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */
46 tlv320aic3007: tlv320aic3007@18 {
47 compatible = "ti,tlv320aic3007";
49 AVDD-supply = <&vcc3v3>;
50 IOVDD-supply = <&vcc3v3>;
51 DRVDD-supply = <&vcc3v3>;
52 DVDD-supply = <&vdig1_reg>;
58 pinctrl-names = "default";
59 pinctrl-0 = <&mcasp0_pins>;
60 op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */
63 2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */
71 ti,model = "AM335x-Wega";
72 ti,audio-codec = <&tlv320aic3007>;
73 ti,mcasp-controller = <&mcasp0>;
79 clocks = <&mcasp0_fck>;
86 dcan1_pins: pinmux_dcan1 {
87 pinctrl-single,pins = <
88 AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
89 AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
95 pinctrl-names = "default";
96 pinctrl-0 = <&dcan1_pins>;
102 ethernet1_pins: pinmux_ethernet1 {
103 pinctrl-single,pins = <
104 AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* gpmc_a0.mii2_txen */
105 AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a1.mii2_rxdv */
106 AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* gpmc_a2.mii2_txd3 */
107 AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1) /* gpmc_a3.mii2_txd2 */
108 AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* gpmc_a4.mii2_txd1 */
109 AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* gpmc_a5.mii2_txd0 */
110 AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a6.mii2_txclk */
111 AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a7.mii2_rxclk */
112 AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a8.mii2_rxd3 */
113 AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a9.mii2_rxd2 */
114 AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a10.mii2_rxd1 */
115 AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a11.mii2_rxd0 */
116 AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_wpn.mii2_rxerr */
117 AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_ben1.mii2_col */
123 phy-handle = <&phy1>;
125 dual_emac_res_vlan = <2>;
129 phy1: ethernet-phy@1 {
136 pinctrl-names = "default";
137 pinctrl-0 = <ðernet0_pins ðernet1_pins>;
143 mmc1_pins: pinmux_mmc1 {
144 pinctrl-single,pins = <
145 AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
146 AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
147 AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
148 AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
149 AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
150 AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
151 AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7) /* spi0_cs1.mmc0_sdcd */
157 vmmc-supply = <&vcc3v3>;
159 pinctrl-names = "default";
160 pinctrl-0 = <&mmc1_pins>;
161 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
173 uart0_pins: pinmux_uart0 {
174 pinctrl-single,pins = <
175 AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
176 AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
180 uart1_pins: pinmux_uart1_pins {
181 pinctrl-single,pins = <
182 AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
183 AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
184 AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
185 AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
191 pinctrl-names = "default";
192 pinctrl-0 = <&uart0_pins>;
197 pinctrl-names = "default";
198 pinctrl-0 = <&uart1_pins>;