1 // SPDX-License-Identifier: GPL-2.0+
5 * EETS GmbH PDU001 board device tree file
7 * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
9 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
14 #include "am33xx.dtsi"
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/leds/leds-pca9532.h>
19 model = "EETS,PDU001";
20 compatible = "eets,pdu001", "ti,am33xx";
28 cpu0-supply = <&vdd1_reg>;
33 device_type = "memory";
34 reg = <0x80000000 0x10000000>; /* 256 MB */
37 vbat: fixedregulator@0 {
38 compatible = "regulator-fixed";
39 regulator-name = "vbat";
40 regulator-min-microvolt = <3600000>;
41 regulator-max-microvolt = <3600000>;
45 lis3_reg: fixedregulator@1 {
46 compatible = "regulator-fixed";
47 regulator-name = "lis3_reg";
52 compatible = "ti,tilcdc,panel";
54 pinctrl-names = "default";
55 pinctrl-0 = <&lcd_pins_s0>;
70 clock-frequency = <6500000>;
81 pixelclk-active = <1>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&clkout2_pin>;
92 i2c0_pins: pinmux_i2c0_pins {
93 pinctrl-single,pins = <
94 AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
95 AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
99 i2c1_pins: pinmux_i2c1_pins {
100 pinctrl-single,pins = <
101 AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
102 AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
106 i2c2_pins: pinmux_i2c2_pins {
107 pinctrl-single,pins = <
108 AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_clk.i2c2_sda */
109 AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d0.i2c2_scl */
113 spi1_pins: pinmux_spi1_pins {
114 pinctrl-single,pins = <
115 AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */
116 AM33XX_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
117 AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
118 AM33XX_IOPAD(0x99C, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
122 uart0_pins: pinmux_uart0_pins {
123 pinctrl-single,pins = <
124 AM33XX_IOPAD(0x96C, PIN_OUTPUT | MUX_MODE7) /* uart0_rtsn.gpio1_9 */
125 AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
126 AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
130 uart1_pins: pinmux_uart1_pins {
131 pinctrl-single,pins = <
132 AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
133 AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
137 uart3_pins: pinmux_uart3_pins {
138 pinctrl-single,pins = <
139 AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE1) /* spi0_cs1.uart3_rxd */
140 AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
144 clkout2_pin: pinmux_clkout2_pin {
145 pinctrl-single,pins = <
146 AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
150 cpsw_default: cpsw_default {
151 pinctrl-single,pins = <
153 AM33XX_IOPAD(0x908, PIN_INPUT | MUX_MODE0) /* mii1_col.mii1_col */
154 AM33XX_IOPAD(0x90C, PIN_INPUT | MUX_MODE0) /* mii1_crs.mii1_crs */
155 AM33XX_IOPAD(0x910, PIN_INPUT | MUX_MODE0) /* mii1_rxer.mii1_rxer */
156 AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE0) /* mii1_txen.mii1_txen */
157 AM33XX_IOPAD(0x918, PIN_INPUT | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
158 AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
159 AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
160 AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
161 AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
162 AM33XX_IOPAD(0x92c, PIN_INPUT | MUX_MODE0) /* mii1_txclk.mii1_txclk */
163 AM33XX_IOPAD(0x930, PIN_INPUT | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
164 AM33XX_IOPAD(0x934, PIN_INPUT | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
165 AM33XX_IOPAD(0x938, PIN_INPUT | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
166 AM33XX_IOPAD(0x93c, PIN_INPUT | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
167 AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
170 AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* mii2_txen.gpmc_a0 */
171 AM33XX_IOPAD(0x844, PIN_INPUT | MUX_MODE1) /* mii2_rxdv.gpmc_a1 */
172 AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* mii2_txd3.gpmc_a2 */
173 AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1) /* mii2_txd2.gpmc_a3 */
174 AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* mii2_txd1.gpmc_a4 */
175 AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* mii2_txd0.gpmc_a5 */
176 AM33XX_IOPAD(0x858, PIN_INPUT | MUX_MODE1) /* mii2_txclk.gpmc_a6 */
177 AM33XX_IOPAD(0x85c, PIN_INPUT | MUX_MODE1) /* mii2_rxclk.gpmc_a7 */
178 AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE1) /* mii2_rxd3.gpmc_a8 */
179 AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE1) /* mii2_rxd2.gpmc_a9 */
180 AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE1) /* mii2_rxd1.gpmc_a10 */
181 AM33XX_IOPAD(0x86C, PIN_INPUT | MUX_MODE1) /* mii2_rxd0.gpmc_a11 */
182 AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE1) /* mii2_crs.gpmc_wait0 */
183 AM33XX_IOPAD(0x874, PIN_INPUT | MUX_MODE1) /* mii2_rxer.gpmc_wpn */
184 AM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE1) /* mii2_col.gpmc_ben1 */
188 davinci_mdio_default: davinci_mdio_default {
189 pinctrl-single,pins = <
190 AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
191 AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
195 mmc1_pins: pinmux_mmc1_pins {
197 pinctrl-single,pins = <
198 AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */
199 AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */
200 AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */
201 AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */
202 AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */
203 AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */
207 mmc2_pins: pinmux_mmc2_pins {
209 pinctrl-single,pins = <
210 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
211 AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
212 AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
213 AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
214 AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
215 AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
216 /* card change signal for frontpanel SD cardcage */
217 AM33XX_IOPAD(0x890, PIN_INPUT | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
221 lcd_pins_s0: lcd_pins_s0 {
222 pinctrl-single,pins = <
223 AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
224 AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
225 AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
226 AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
227 AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
228 AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
229 AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
230 AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
231 AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
232 AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
233 AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
234 AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
235 AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
236 AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
237 AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
238 AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
239 AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
240 AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
241 AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
242 AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
246 dcan0_pins: pinmux_dcan0_pins {
247 pinctrl-single,pins = <
248 AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
249 AM33XX_IOPAD(0x97c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
255 pinctrl-names = "default";
256 pinctrl-0 = <&uart0_pins>;
258 rts-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
259 rs485-rts-active-high;
260 rs485-rts-delay = <0 0>;
261 linux,rs485-enabled-at-boot-time;
267 pinctrl-names = "default";
268 pinctrl-0 = <&uart1_pins>;
274 pinctrl-names = "default";
275 pinctrl-0 = <&uart3_pins>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&i2c0_pins>;
285 clock-frequency = <400000>;
291 m2_eeprom: m2_eeprom@50 {
292 compatible = "atmel,24c256";
299 pinctrl-names = "default";
300 pinctrl-0 = <&i2c1_pins>;
303 clock-frequency = <100000>;
305 board_24aa025e48: board_24aa025e48@50 {
306 compatible = "microchip,24aa025e48";
310 backplane_24aa025e48: backplane_24aa025e48@53 {
311 compatible = "microchip,24aa025e48";
315 pca9532: pca9532@60 {
316 compatible = "nxp,pca9532";
324 type = <PCA9532_TYPE_LED>;
327 type = <PCA9532_TYPE_LED>;
328 default-state = "on";
331 type = <PCA9532_TYPE_LED>;
334 type = <PCA9532_TYPE_LED>;
337 type = <PCA9532_TYPE_LED>;
340 type = <PCA9532_TYPE_LED>;
344 pca9530: pca9530@61 {
345 compatible = "nxp,pca9530";
349 type = <PCA9532_TYPE_LED>;
350 linux,default-trigger = "backlight";
351 default-state = "on";
355 mcp79400: mcp79400@6f {
356 compatible = "microchip,mcp7940x";
362 pinctrl-names = "default";
363 pinctrl-0 = <&i2c2_pins>;
366 clock-frequency = <100000>;
370 pinctrl-names = "default";
371 pinctrl-0 = <&spi1_pins>;
372 ti,pindir-d0-out-d1-in;
376 compatible = "orise,otm3225a";
378 spi-max-frequency = <1000000>;
415 * Disable soc's rtc as we have no VBAT for it. This makes the board
416 * rtc (Microchip MCP79400) the default rtc device 'rtc0'.
430 #include "tps65910.dtsi"
433 vcc1-supply = <&vbat>;
434 vcc2-supply = <&vbat>;
435 vcc3-supply = <&vbat>;
436 vcc4-supply = <&vbat>;
437 vcc5-supply = <&vbat>;
438 vcc6-supply = <&vbat>;
439 vcc7-supply = <&vbat>;
440 vccio-supply = <&vbat>;
443 vrtc_reg: regulator@0 {
444 regulator-name = "ldo_vrtc";
448 vio_reg: regulator@1 {
449 regulator-name = "buck_vdd_ddr";
453 vdd1_reg: regulator@2 {
454 /* VDD_MPU voltage limits */
455 regulator-name = "buck_vdd_mpu";
456 regulator-min-microvolt = <912500>;
457 regulator-max-microvolt = <1312500>;
462 vdd2_reg: regulator@3 {
463 /* VDD_CORE voltage limits */
464 regulator-name = "buck_vdd_core";
465 regulator-min-microvolt = <912500>;
466 regulator-max-microvolt = <1150000>;
471 vdd3_reg: regulator@4 {
472 regulator-name = "boost_res";
476 vdig1_reg: regulator@5 {
477 regulator-name = "ldo_vdig1";
481 vdig2_reg: regulator@6 {
482 regulator-name = "ldo_vdig2";
486 vpll_reg: regulator@7 {
487 regulator-name = "ldo_vpll";
491 vdac_reg: regulator@8 {
492 regulator-name = "ldo_vdac";
496 vaux1_reg: regulator@9 {
497 regulator-name = "ldo_vaux1";
501 vaux2_reg: regulator@10 {
502 regulator-name = "ldo_vaux2";
506 vaux33_reg: regulator@11 {
507 regulator-name = "ldo_vaux33";
511 vmmc_reg: regulator@12 {
512 regulator-name = "ldo_vmmc";
513 regulator-min-microvolt = <1800000>;
514 regulator-max-microvolt = <3300000>;
518 vbb_reg: regulator@13 {
519 regulator-name = "bat_vbb";
525 pinctrl-names = "default";
526 pinctrl-0 = <&cpsw_default>;
527 dual_emac; /* no switch, two distinct MACs */
532 pinctrl-names = "default";
533 pinctrl-0 = <&davinci_mdio_default>;
538 phy_id = <&davinci_mdio>, <0>;
540 dual_emac_res_vlan = <1>;
544 phy_id = <&davinci_mdio>, <1>;
546 dual_emac_res_vlan = <2>;
553 ti,x-plate-resistance = <200>;
554 ti,coordinate-readouts = <5>;
555 ti,wire-config = <0x01 0x10 0x22 0x33>;
556 ti,charge-delay = <0x400>;
560 ti,adc-channels = <4 5 6 7>;
566 vmmc-supply = <&vmmc_reg>;
568 pinctrl-names = "default";
569 pinctrl-0 = <&mmc1_pins>;
575 vmmc-supply = <&vmmc_reg>;
577 pinctrl-names = "default";
578 pinctrl-0 = <&mmc2_pins>;
579 cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
592 pinctrl-names = "default";
593 pinctrl-0 = <&dcan0_pins>;