2 * Common support for Siemens Draco SOM (AM335x based)
4 * Copyright (C) 2013,2014 - Stefan Roese <sr@denx.de>
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
18 device_type = "memory";
19 reg = <0x80000000 0x08000000>; /* 128 MB */
23 uart0: serial@44e09000 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&uart0_pins>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&i2c0_pins>;
34 clock-frequency = <400000>;
37 compatible = "atmel,24c128";
67 dma-controller@47402000 {
75 i2c0_pins: pinmux_i2c0_pins {
76 pinctrl-single,pins = <
77 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
78 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
82 uart0_pins: pinmux_uart0_pins {
83 pinctrl-single,pins = <
84 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
85 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
89 nandflash_pins: nandflash_pins {
90 pinctrl-single,pins = <
91 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
92 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
93 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
94 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
95 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
96 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
97 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
98 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
99 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
100 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
101 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
102 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
103 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
104 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
105 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
125 pinctrl-names = "default";
126 pinctrl-0 = <&nandflash_pins>;
128 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
131 reg = <0 0 0>; /* CS0, offset 0 */
132 nand-bus-width = <8>;
133 ti,nand-ecc-opt = "bch8";
134 gpmc,device-nand = "true";
135 gpmc,device-width = <1>;
136 gpmc,sync-clk-ps = <0>;
138 gpmc,cs-rd-off-ns = <44>;
139 gpmc,cs-wr-off-ns = <44>;
140 gpmc,adv-on-ns = <6>;
141 gpmc,adv-rd-off-ns = <34>;
142 gpmc,adv-wr-off-ns = <44>;
144 gpmc,we-off-ns = <40>;
146 gpmc,oe-off-ns = <54>;
147 gpmc,access-ns = <64>;
148 gpmc,rd-cycle-ns = <82>;
149 gpmc,wr-cycle-ns = <82>;
150 gpmc,wait-on-read = "true";
151 gpmc,wait-on-write = "true";
152 gpmc,bus-turnaround-ns = <0>;
153 gpmc,cycle2cycle-delay-ns = <0>;
154 gpmc,clk-activation-ns = <0>;
155 gpmc,wait-monitoring-ns = <0>;
156 gpmc,wr-access-ns = <40>;
157 gpmc,wr-data-mux-bus-ns = <0>;
159 #address-cells = <1>;
165 /* disable the RTC node as its not accessible on the draco/dxr2 board */
168 ti,hwmods = "disabled";