2 * Copyright (c) 2011 The Chromium OS Authors.
3 * See file CREDITS for list of people who contributed to this
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 /* Tegra20 Clock control functions */
26 #include <asm/arch/clock.h>
27 #include <asm/arch/tegra.h>
28 #include <asm/arch-tegra/clk_rst.h>
29 #include <asm/arch-tegra/timer.h>
34 * Clock types that we can use as a source. The Tegra20 has muxes for the
35 * peripheral clocks, and in most cases there are four options for the clock
36 * source. This gives us a clock 'type' and exploits what commonality exists
39 * Letters are obvious, except for T which means CLK_M, and S which means the
40 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
41 * datasheet) and PLL_M are different things. The former is the basic
42 * clock supplied to the SOC from an external oscillator. The latter is the
45 * See definitions in clock_id in the header file.
48 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
49 CLOCK_TYPE_MCPA, /* and so on */
53 CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */
58 CLOCK_TYPE_NONE = -1, /* invalid clock type */
62 CLOCK_MAX_MUX = 4 /* number of source options for each clock */
66 * Clock source mux for each clock type. This just converts our enum into
67 * a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS
68 * is special as it has 5 sources. Since it also has a different number of
69 * bits in its register for the source, we just handle it with a special
72 #define CLK(x) CLOCK_ID_ ## x
73 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
74 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
75 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) },
76 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
77 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) },
78 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
79 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
80 { CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
81 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
85 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is
86 * not in the header file since it is for purely internal use - we want
87 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
88 * confusion bewteen PERIPH_ID_... and PERIPHC_...
90 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
93 * Note to SOC vendors: perhaps define a unified numbering for peripherals and
94 * use it for reset, clock enable, clock source/divider and even pinmuxing
97 enum periphc_internal_id {
114 PERIPHC_10, /* PERIPHC_SPI1, what is this really? */
172 * Clock type for each peripheral clock source. We put the name in each
173 * record just so it is easy to match things up
175 #define TYPE(name, type) type
176 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
178 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
179 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
180 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
181 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
182 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCXTS),
183 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
184 TYPE(PERIPHC_SPI22, CLOCK_TYPE_PCMT),
185 TYPE(PERIPHC_SPI3, CLOCK_TYPE_PCMT),
188 TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT),
189 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
190 TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
191 TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT),
192 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
193 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
194 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDCT),
195 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDCT),
198 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
199 TYPE(PERIPHC_IDE0, CLOCK_TYPE_PCMT),
200 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
201 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
202 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
203 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
204 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
205 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
208 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
209 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
210 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
211 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
212 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
213 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT),
214 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
215 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
218 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
219 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
220 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
221 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT),
222 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
223 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
224 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
225 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
228 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
229 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
230 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
231 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
232 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
233 TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT),
234 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
235 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
238 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
239 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
240 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
241 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
242 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
243 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
247 * This array translates a periph_id to a periphc_internal_id
249 * Not present/matched up:
250 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
251 * SPDIF - which is both 0x08 and 0x0c
254 #define NONE(name) (-1)
255 #define OFFSET(name, value) PERIPHC_ ## name
256 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
265 PERIPHC_UART2, /* and vfir 0x68 */
270 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
297 /* Middle word: 63:32 */
309 NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
319 PERIPHC_TVO, /* also CVE 0x40 */
337 /* Upper word 95:64 */
372 * Get the oscillator frequency, from the corresponding hardware configuration
373 * field. T20 has 4 frequencies that it supports.
375 enum clock_osc_freq clock_get_osc_freq(void)
377 struct clk_rst_ctlr *clkrst =
378 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
381 reg = readl(&clkrst->crc_osc_ctrl);
382 return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
385 /* Returns a pointer to the clock source register for a peripheral */
386 u32 *get_periph_source_reg(enum periph_id periph_id)
388 struct clk_rst_ctlr *clkrst =
389 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
390 enum periphc_internal_id internal_id;
392 assert(clock_periph_id_isvalid(periph_id));
393 internal_id = periph_id_to_internal_id[periph_id];
394 assert(internal_id != -1);
395 return &clkrst->crc_clk_src[internal_id];
399 * Given a peripheral ID and the required source clock, this returns which
400 * value should be programmed into the source mux for that peripheral.
402 * There is special code here to handle the one source type with 5 sources.
404 * @param periph_id peripheral to start
405 * @param source PLL id of required parent clock
406 * @param mux_bits Set to number of bits in mux register: 2 or 4
407 * @param divider_bits Set to number of divider bits (8 or 16)
408 * @return mux value (0-4, or -1 if not found)
410 int get_periph_clock_source(enum periph_id periph_id,
411 enum clock_id parent, int *mux_bits, int *divider_bits)
413 enum clock_type_id type;
414 enum periphc_internal_id internal_id;
417 assert(clock_periph_id_isvalid(periph_id));
419 internal_id = periph_id_to_internal_id[periph_id];
420 assert(periphc_internal_id_isvalid(internal_id));
422 type = clock_periph_type[internal_id];
423 assert(clock_type_id_isvalid(type));
426 * Special cases here for the clock with a 4-bit source mux and I2C
427 * with its 16-bit divisor
429 if (type == CLOCK_TYPE_PCXTS)
433 if (type == CLOCK_TYPE_PCMT16)
438 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
439 if (clock_source[type][mux] == parent)
443 * Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS
444 * which is not in our table. If not, then they are asking for a
445 * source which this peripheral can't access through its mux.
447 assert(type == CLOCK_TYPE_PCXTS);
448 assert(parent == CLOCK_ID_SFROM32KHZ);
449 if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
450 return 4; /* mux value for this clock */
452 /* if we get here, either us or the caller has made a mistake */
453 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
458 void clock_set_enable(enum periph_id periph_id, int enable)
460 struct clk_rst_ctlr *clkrst =
461 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
462 u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
465 /* Enable/disable the clock to this peripheral */
466 assert(clock_periph_id_isvalid(periph_id));
469 reg |= PERIPH_MASK(periph_id);
471 reg &= ~PERIPH_MASK(periph_id);
475 void reset_set_enable(enum periph_id periph_id, int enable)
477 struct clk_rst_ctlr *clkrst =
478 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
479 u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
482 /* Enable/disable reset to the peripheral */
483 assert(clock_periph_id_isvalid(periph_id));
486 reg |= PERIPH_MASK(periph_id);
488 reg &= ~PERIPH_MASK(periph_id);
492 #ifdef CONFIG_OF_CONTROL
494 * Convert a device tree clock ID to our peripheral ID. They are mostly
495 * the same but we are very cautious so we check that a valid clock ID is
498 * @param clk_id Clock ID according to tegra20 device tree binding
499 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
501 enum periph_id clk_id_to_periph_id(int clk_id)
503 if (clk_id > PERIPH_ID_COUNT)
504 return PERIPH_ID_NONE;
507 case PERIPH_ID_RESERVED1:
508 case PERIPH_ID_RESERVED2:
509 case PERIPH_ID_RESERVED30:
510 case PERIPH_ID_RESERVED35:
511 case PERIPH_ID_RESERVED56:
512 case PERIPH_ID_RESERVED74:
513 case PERIPH_ID_RESERVED76:
514 case PERIPH_ID_RESERVED77:
515 case PERIPH_ID_RESERVED78:
516 case PERIPH_ID_RESERVED79:
517 case PERIPH_ID_RESERVED80:
518 case PERIPH_ID_RESERVED81:
519 case PERIPH_ID_RESERVED82:
520 case PERIPH_ID_RESERVED83:
521 case PERIPH_ID_RESERVED91:
522 return PERIPH_ID_NONE;
527 #endif /* CONFIG_OF_CONTROL */
529 void clock_early_init(void)
532 * PLLP output frequency set to 216MHz
533 * PLLC output frequency set to 600Mhz
535 * TODO: Can we calculate these values instead of hard-coding?
537 switch (clock_get_osc_freq()) {
538 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
539 clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
540 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
543 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
544 clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
545 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
548 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
549 clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8);
550 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
552 case CLOCK_OSC_FREQ_19_2:
555 * These are not supported. It is too early to print a
556 * message and the UART likely won't work anyway due to the
557 * oscillator being wrong.