2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 /* Tegra114 Clock control functions */
21 #include <asm/arch/clock.h>
22 #include <asm/arch/sysctr.h>
23 #include <asm/arch/tegra.h>
24 #include <asm/arch-tegra/clk_rst.h>
25 #include <asm/arch-tegra/timer.h>
30 * Clock types that we can use as a source. The Tegra114 has muxes for the
31 * peripheral clocks, and in most cases there are four options for the clock
32 * source. This gives us a clock 'type' and exploits what commonality exists
35 * Letters are obvious, except for T which means CLK_M, and S which means the
36 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
37 * datasheet) and PLL_M are different things. The former is the basic
38 * clock supplied to the SOC from an external oscillator. The latter is the
41 * See definitions in clock_id in the header file.
44 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
45 CLOCK_TYPE_MCPA, /* and so on */
57 CLOCK_TYPE_NONE = -1, /* invalid clock type */
61 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
65 MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */
71 * Clock source mux for each clock type. This just converts our enum into
72 * a list of mux sources for use by the code.
75 * The extra column in each clock source array is used to store the mask
76 * bits in its register for the source.
78 #define CLK(x) CLOCK_ID_ ## x
79 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
80 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
81 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
83 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
84 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
86 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
87 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
89 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
90 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
92 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
93 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
95 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
96 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
98 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
99 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
101 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
102 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
104 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
105 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
107 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
108 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
110 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
111 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
116 * Clock type for each peripheral clock source. We put the name in each
117 * record just so it is easy to match things up
119 #define TYPE(name, type) type
120 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
122 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
123 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
124 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
125 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
126 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */
127 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
128 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
129 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
132 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
133 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
134 TYPE(PERIPHC_I2C5, CLOCK_TYPE_PCMT16),
135 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
136 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
137 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
138 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
139 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
142 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
143 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
144 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
145 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
146 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
147 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
148 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
149 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
152 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
153 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
154 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
155 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
156 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
157 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
158 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
159 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
162 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
163 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
164 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
165 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
166 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
167 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
168 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
169 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
172 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
173 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
174 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
175 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
176 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
177 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
178 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
179 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
182 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
183 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
184 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
185 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
186 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
187 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
188 TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
189 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
191 /* 0x38h */ /* Jumps to reg offset 0x3B0h */
192 TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
193 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
194 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */
195 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
196 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
197 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16),
198 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
199 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
202 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
203 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
204 TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
205 TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
206 TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
207 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
208 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */
209 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
212 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
213 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
214 TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
215 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */
216 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
217 TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
218 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
219 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
222 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
223 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
224 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
225 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
226 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */
227 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
228 TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
232 * This array translates a periph_id to a periphc_internal_id
234 * Not present/matched up:
235 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
236 * SPDIF - which is both 0x08 and 0x0c
239 #define NONE(name) (-1)
240 #define OFFSET(name, value) PERIPHC_ ## name
241 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
250 PERIPHC_UART2, /* and vfir 0x68 */
255 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
282 /* Middle word: 63:32 */
294 NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
304 PERIPHC_TVO, /* also CVE 0x40 */
322 /* Upper word 95:64 */
404 NONE(RESERVED1_SATACOLD),
405 NONE(RESERVED2_PCIERX0),
406 NONE(RESERVED3_PCIERX1),
407 NONE(RESERVED4_PCIERX2),
408 NONE(RESERVED5_PCIERX3),
409 NONE(RESERVED6_PCIERX4),
410 NONE(RESERVED7_PCIERX5),
428 NONE(RESERVED21_ENTROPY),
444 * Get the oscillator frequency, from the corresponding hardware configuration
445 * field. Note that T30/T114 support 3 new higher freqs, but we map back
446 * to the old T20 freqs. Support for the higher oscillators is TBD.
448 enum clock_osc_freq clock_get_osc_freq(void)
450 struct clk_rst_ctlr *clkrst =
451 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
454 reg = readl(&clkrst->crc_osc_ctrl);
455 reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
457 if (reg & 1) /* one of the newer freqs */
458 printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
460 return reg >> 2; /* Map to most common (T20) freqs */
463 /* Returns a pointer to the clock source register for a peripheral */
464 u32 *get_periph_source_reg(enum periph_id periph_id)
466 struct clk_rst_ctlr *clkrst =
467 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
468 enum periphc_internal_id internal_id;
470 /* Coresight is a special case */
471 if (periph_id == PERIPH_ID_CSI)
472 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
474 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
475 internal_id = periph_id_to_internal_id[periph_id];
476 assert(internal_id != -1);
477 if (internal_id >= PERIPHC_VW_FIRST) {
478 internal_id -= PERIPHC_VW_FIRST;
479 return &clkrst->crc_clk_src_vw[internal_id];
481 return &clkrst->crc_clk_src[internal_id];
485 * Given a peripheral ID and the required source clock, this returns which
486 * value should be programmed into the source mux for that peripheral.
488 * There is special code here to handle the one source type with 5 sources.
490 * @param periph_id peripheral to start
491 * @param source PLL id of required parent clock
492 * @param mux_bits Set to number of bits in mux register: 2 or 4
493 * @param divider_bits Set to number of divider bits (8 or 16)
494 * @return mux value (0-4, or -1 if not found)
496 int get_periph_clock_source(enum periph_id periph_id,
497 enum clock_id parent, int *mux_bits, int *divider_bits)
499 enum clock_type_id type;
500 enum periphc_internal_id internal_id;
503 assert(clock_periph_id_isvalid(periph_id));
505 internal_id = periph_id_to_internal_id[periph_id];
506 assert(periphc_internal_id_isvalid(internal_id));
508 type = clock_periph_type[internal_id];
509 assert(clock_type_id_isvalid(type));
511 *mux_bits = clock_source[type][CLOCK_MAX_MUX];
513 if (type == CLOCK_TYPE_PCMT16)
518 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
519 if (clock_source[type][mux] == parent)
522 /* if we get here, either us or the caller has made a mistake */
523 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
528 void clock_set_enable(enum periph_id periph_id, int enable)
530 struct clk_rst_ctlr *clkrst =
531 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
535 /* Enable/disable the clock to this peripheral */
536 assert(clock_periph_id_isvalid(periph_id));
537 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
538 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
540 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
543 reg |= PERIPH_MASK(periph_id);
545 reg &= ~PERIPH_MASK(periph_id);
549 void reset_set_enable(enum periph_id periph_id, int enable)
551 struct clk_rst_ctlr *clkrst =
552 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
556 /* Enable/disable reset to the peripheral */
557 assert(clock_periph_id_isvalid(periph_id));
558 if (periph_id < PERIPH_ID_VW_FIRST)
559 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
561 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
564 reg |= PERIPH_MASK(periph_id);
566 reg &= ~PERIPH_MASK(periph_id);
570 #ifdef CONFIG_OF_CONTROL
572 * Convert a device tree clock ID to our peripheral ID. They are mostly
573 * the same but we are very cautious so we check that a valid clock ID is
576 * @param clk_id Clock ID according to tegra114 device tree binding
577 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
579 enum periph_id clk_id_to_periph_id(int clk_id)
581 if (clk_id > PERIPH_ID_COUNT)
582 return PERIPH_ID_NONE;
585 case PERIPH_ID_RESERVED3:
586 case PERIPH_ID_RESERVED16:
587 case PERIPH_ID_RESERVED24:
588 case PERIPH_ID_RESERVED35:
589 case PERIPH_ID_RESERVED43:
590 case PERIPH_ID_RESERVED45:
591 case PERIPH_ID_RESERVED56:
592 case PERIPH_ID_RESERVED76:
593 case PERIPH_ID_RESERVED77:
594 case PERIPH_ID_RESERVED78:
595 case PERIPH_ID_RESERVED83:
596 case PERIPH_ID_RESERVED89:
597 case PERIPH_ID_RESERVED91:
598 case PERIPH_ID_RESERVED93:
599 case PERIPH_ID_RESERVED94:
600 case PERIPH_ID_RESERVED95:
601 return PERIPH_ID_NONE;
606 #endif /* CONFIG_OF_CONTROL */
608 void clock_early_init(void)
610 struct clk_rst_ctlr *clkrst =
611 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
614 * PLLP output frequency set to 408Mhz
615 * PLLC output frequency set to 600Mhz
616 * PLLD output frequency set to 925Mhz
618 switch (clock_get_osc_freq()) {
619 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
620 clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
621 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
622 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
625 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
626 clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
627 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
628 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
631 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
632 clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
633 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
634 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
636 case CLOCK_OSC_FREQ_19_2:
639 * These are not supported. It is too early to print a
640 * message and the UART likely won't work anyway due to the
641 * oscillator being wrong.
646 /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
647 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
649 /* PLLC_MISC: Set LOCK_ENABLE */
650 writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc);
653 /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */
654 writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
658 void arch_timer_init(void)
660 struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
663 freq = clock_get_rate(CLOCK_ID_OSC);
664 debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
667 asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
669 /* Only T114 has the System Counter regs */
670 debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
671 writel(freq, &sysctr->cntfid0);
673 val = readl(&sysctr->cntcr);
674 val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
675 writel(val, &sysctr->cntcr);
676 debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);