2 * Startup Code for S3C44B0 CPU-core
7 * http://www.dave-tech.it
8 * http://www.wawnet.biz
9 * mailto:info@wawnet.biz
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm-offsets.h>
41 add pc, pc, #0x0c000000
42 add pc, pc, #0x0c000000
43 add pc, pc, #0x0c000000
44 add pc, pc, #0x0c000000
45 add pc, pc, #0x0c000000
46 add pc, pc, #0x0c000000
47 add pc, pc, #0x0c000000
49 .balignl 16,0xdeadbeef
53 *************************************************************************
55 * Startup Code (reset vector)
57 * do important init only if we don't start from memory!
58 * relocate u-boot to ram
60 * jump to second stage
62 *************************************************************************
67 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
68 .word CONFIG_SPL_TEXT_BASE
70 .word CONFIG_SYS_TEXT_BASE
74 * These are defined in the board-specific linker script.
75 * Subtracting _start from them lets the linker put their
76 * relative position in the executable instead of leaving
81 .word __bss_start - _start
85 .word __bss_end - _start
92 /* IRQ stack memory (calculated at run-time) */
93 .globl IRQ_STACK_START
97 /* IRQ stack memory (calculated at run-time) */
98 .globl FIQ_STACK_START
103 /* IRQ stack memory (calculated at run-time) + 8 bytes */
104 .globl IRQ_STACK_START_IN
109 * the actual reset code
114 * set the cpu to SVC32 mode
122 * we do sys-critical inits only at reboot,
123 * not when booting from ram!
125 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
128 * before relocating, we have to setup RAM timing
129 * because memory timing is board-dependend, you will
130 * find a lowlevel_init.S in your board directory.
137 /*------------------------------------------------------------------------------*/
139 .globl c_runtime_cpu_setup
145 *************************************************************************
147 * CPU_init_critical registers
149 * setup important registers
150 * setup memory timing
152 *************************************************************************
155 #define INTCON (0x01c00000+0x200000)
156 #define INTMSK (0x01c00000+0x20000c)
157 #define LOCKTIME (0x01c00000+0x18000c)
158 #define PLLCON (0x01c00000+0x180000)
159 #define CLKCON (0x01c00000+0x180004)
160 #define WTCON (0x01c00000+0x130000)
162 /* disable watch dog */
168 * mask all IRQs by clearing all bits in the INTMRs
178 /* Set Clock Control Register */
185 #if CONFIG_S3C44B0_CLOCK_SPEED==66
186 ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
187 #elif CONFIG_S3C44B0_CLOCK_SPEED==75
188 ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */
190 # error CONFIG_S3C44B0_CLOCK_SPEED undefined
202 /*************************************************/
203 /* interrupt vectors */
204 /*************************************************/
207 b undefined_instruction
215 /*************************************************/
217 undefined_instruction:
234 /* we *should* never reach this */