2 * armboot - Startup Code for XScale CPU-core
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
8 * Copyright (C) 2001 Marius Groger <mag@sysgo.de>
9 * Copyright (C) 2002 Alex Zupke <azu@sysgo.de>
10 * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de>
11 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
12 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
13 * Copyright (C) 2003 Kshitij <kshitij@ti.com>
14 * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com>
15 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
16 * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com>
17 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
19 * See file CREDITS for list of people who contributed to this
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License as
24 * published by the Free Software Foundation; either version 2 of
25 * the License, or (at your option) any later version.
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
38 #include <asm-offsets.h>
42 #ifdef CONFIG_CPU_PXA25X
43 #if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
44 #error "Init SP address must be set to 0xfffff800 for PXA250"
50 #ifdef CONFIG_SPL_BUILD
67 .word 0x12345678 /* now 16*4=64 */
69 ldr pc, _undefined_instruction
70 ldr pc, _software_interrupt
71 ldr pc, _prefetch_abort
77 _undefined_instruction: .word undefined_instruction
78 _software_interrupt: .word software_interrupt
79 _prefetch_abort: .word prefetch_abort
80 _data_abort: .word data_abort
81 _not_used: .word not_used
84 _pad: .word 0x12345678 /* now 16*4=64 */
85 #endif /* CONFIG_SPL_BUILD */
89 .balignl 16,0xdeadbeef
91 *************************************************************************
93 * Startup Code (reset vector)
95 * do important init only if we don't start from memory!
96 * setup Memory and board specific bits prior to relocation.
97 * relocate armboot to ram
100 *************************************************************************
105 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
106 .word CONFIG_SPL_TEXT_BASE
108 .word CONFIG_SYS_TEXT_BASE
112 * These are defined in the board-specific linker script.
113 * Subtracting _start from them lets the linker put their
114 * relative position in the executable instead of leaving
117 .globl _bss_start_ofs
119 .word __bss_start - _start
123 .word __bss_end - _start
129 #ifdef CONFIG_USE_IRQ
130 /* IRQ stack memory (calculated at run-time) */
131 .globl IRQ_STACK_START
135 /* IRQ stack memory (calculated at run-time) */
136 .globl FIQ_STACK_START
141 /* IRQ stack memory (calculated at run-time) + 8 bytes */
142 .globl IRQ_STACK_START_IN
147 * the actual reset code
152 * set the cpu to SVC32 mode
159 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
163 #ifdef CONFIG_CPU_PXA25X
164 bl lock_cache_for_stack
169 /*------------------------------------------------------------------------------*/
170 #ifndef CONFIG_SPL_BUILD
172 * void relocate_code (addr_sp, gd, addr_moni)
174 * This function relocates the monitor code.
178 mov r4, r0 /* save addr_sp */
179 mov r5, r1 /* save addr of gd */
180 mov r6, r2 /* save addr of destination */
182 /* Disable the Dcache RAM lock for stack now */
183 #ifdef CONFIG_CPU_PXA25X
190 subs r9, r6, r0 /* r9 <- relocation offset */
191 beq relocate_done /* skip relocation */
192 mov r1, r6 /* r1 <- scratch for copy_loop */
193 ldr r3, _bss_start_ofs
194 add r2, r0, r3 /* r2 <- source end address */
197 ldmia r0!, {r10-r11} /* copy from source address [r0] */
198 stmia r1!, {r10-r11} /* copy to target address [r1] */
199 cmp r0, r2 /* until source end address [r2] */
202 #ifndef CONFIG_SPL_BUILD
204 * fix .rel.dyn relocations
206 ldr r0, _TEXT_BASE /* r0 <- Text base */
207 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
208 add r10, r10, r0 /* r10 <- sym table in FLASH */
209 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
210 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
211 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
212 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
214 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
215 add r0, r0, r9 /* r0 <- location to fix up in RAM */
218 cmp r7, #23 /* relative fixup? */
220 cmp r7, #2 /* absolute fixup? */
222 /* ignore unknown type of fixup */
225 /* absolute fix: set location to (offset) symbol value */
226 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
227 add r1, r10, r1 /* r1 <- address of symbol in table */
228 ldr r1, [r1, #4] /* r1 <- symbol value */
229 add r1, r1, r9 /* r1 <- relocated sym addr */
232 /* relative fix: increase location by offset */
237 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
247 .word __rel_dyn_start - _start
249 .word __rel_dyn_end - _start
251 .word __dynsym_start - _start
255 .globl c_runtime_cpu_setup
261 *************************************************************************
263 * CPU_init_critical registers
265 * setup important registers
266 * setup memory timing
268 *************************************************************************
270 #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
273 * flush v4 I/D caches
276 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
277 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
280 * disable MMU stuff and caches
282 mrc p15, 0, r0, c1, c0, 0
283 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
284 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
285 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
286 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
287 mcr p15, 0, r0, c1, c0, 0
289 mov pc, lr /* back to my caller */
290 #endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
292 #ifndef CONFIG_SPL_BUILD
294 *************************************************************************
298 *************************************************************************
303 #define S_FRAME_SIZE 72
325 #define MODE_SVC 0x13
329 * use bad_save_user_regs for abort/prefetch/undef/swi ...
330 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
333 .macro bad_save_user_regs
334 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
335 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
337 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
338 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
339 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
343 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
344 mov r0, sp @ save current stack into r0 (param register)
347 .macro irq_save_user_regs
348 sub sp, sp, #S_FRAME_SIZE
349 stmia sp, {r0 - r12} @ Calling r0-r12
350 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
351 stmdb r8, {sp, lr}^ @ Calling SP, LR
352 str lr, [r8, #0] @ Save calling PC
354 str r6, [r8, #4] @ Save CPSR
355 str r0, [r8, #8] @ Save OLD_R0
359 .macro irq_restore_user_regs
360 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
362 ldr lr, [sp, #S_PC] @ Get PC
363 add sp, sp, #S_FRAME_SIZE
364 subs pc, lr, #4 @ return & move spsr_svc into cpsr
368 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
370 str lr, [r13] @ save caller lr in position 0 of saved stack
371 mrs lr, spsr @ get the spsr
372 str lr, [r13, #4] @ save spsr in position 1 of saved stack
374 mov r13, #MODE_SVC @ prepare SVC-Mode
376 msr spsr, r13 @ switch modes, make sure moves will execute
377 mov lr, pc @ capture return pc
378 movs pc, lr @ jump to next instruction & switch modes.
381 .macro get_bad_stack_swi
382 sub r13, r13, #4 @ space on current stack for scratch reg.
383 str r0, [r13] @ save R0's value.
384 ldr r0, IRQ_STACK_START_IN @ get data regions start
385 str lr, [r0] @ save caller lr in position 0 of saved stack
386 mrs r0, spsr @ get the spsr
387 str lr, [r0, #4] @ save spsr in position 1 of saved stack
388 ldr r0, [r13] @ restore r0
389 add r13, r13, #4 @ pop stack entry
392 .macro get_irq_stack @ setup IRQ stack
393 ldr sp, IRQ_STACK_START
396 .macro get_fiq_stack @ setup FIQ stack
397 ldr sp, FIQ_STACK_START
399 #endif /* CONFIG_SPL_BUILD */
404 #ifdef CONFIG_SPL_BUILD
407 ldr sp, _TEXT_BASE /* use 32 words about stack */
408 bl hang /* hang and never return */
409 #else /* !CONFIG_SPL_BUILD */
411 undefined_instruction:
414 bl do_undefined_instruction
420 bl do_software_interrupt
440 #ifdef CONFIG_USE_IRQ
447 irq_restore_user_regs
452 /* someone ought to write a more effiction fiq_save_user_regs */
455 irq_restore_user_regs
473 #endif /* CONFIG_SPL_BUILD */
477 * Enable MMU to use DCache as DRAM.
479 * This is useful on PXA25x and PXA26x in early bootstages, where there is no
480 * other possible memory available to hold stack.
482 #ifdef CONFIG_CPU_PXA25X
484 mrc p15, 0, \reg, c2, c0, 0
488 lock_cache_for_stack:
489 /* Domain access -- enable for all CPs */
491 mcr p15, 0, r0, c3, c0, 0
493 /* Point TTBR to MMU table */
495 mcr p15, 0, r0, c2, c0, 0
497 /* Kick in MMU, ICache, DCache, BTB */
498 mrc p15, 0, r0, c1, c0, 0
503 mcr p15, 0, r0, c1, c0, 0
506 /* Unlock Icache, Dcache */
507 mcr p15, 0, r0, c9, c1, 1
508 mcr p15, 0, r0, c9, c2, 1
510 /* Flush Icache, Dcache, BTB */
511 mcr p15, 0, r0, c7, c7, 0
513 /* Unlock I-TLB, D-TLB */
514 mcr p15, 0, r0, c10, c4, 1
515 mcr p15, 0, r0, c10, c8, 1
518 mcr p15, 0, r0, c8, c7, 0
520 /* Allocate 4096 bytes of Dcache as RAM */
522 /* Drain pending loads and stores */
523 mcr p15, 0, r0, c7, c10, 4
528 mcr p15, 0, r0, c9, c2, 0
531 /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
536 mcr p15, 0, r1, c7, c2, 5
537 /* Drain pending loads and stores */
538 mcr p15, 0, r0, c7, c10, 4
545 /* Drain pending loads and stores */
546 mcr p15, 0, r0, c7, c10, 4
548 mcr p15, 0, r2, c9, c2, 0
553 .section .mmutable, "a"
556 /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
559 .word (__base << 20) | 0xc12
560 .set __base, __base + 1
563 /* 0xfff00000 : 1:1, cached mapping */
564 .word (0xfff << 20) | 0x1c1e
565 #endif /* CONFIG_CPU_PXA25X */