2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm-offsets.h>
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
50 _undefined_instruction: .word undefined_instruction
51 _software_interrupt: .word software_interrupt
52 _prefetch_abort: .word prefetch_abort
53 _data_abort: .word data_abort
54 _not_used: .word not_used
58 .balignl 16,0xdeadbeef
62 *************************************************************************
64 * Startup Code (reset vector)
66 * do important init only if we don't start from memory!
67 * relocate armboot to ram
69 * jump to second stage
71 *************************************************************************
76 .word CONFIG_SYS_TEXT_BASE
79 * These are defined in the board-specific linker script.
90 /* IRQ stack memory (calculated at run-time) */
91 .globl IRQ_STACK_START
95 /* IRQ stack memory (calculated at run-time) */
96 .globl FIQ_STACK_START
101 /* IRQ stack memory (calculated at run-time) + 8 bytes */
102 .globl IRQ_STACK_START_IN
106 .globl _datarel_start
108 .word __datarel_start
110 .globl _datarelrolocal_start
111 _datarelrolocal_start:
112 .word __datarelrolocal_start
114 .globl _datarellocal_start
116 .word __datarellocal_start
118 .globl _datarelro_start
120 .word __datarelro_start
131 * the actual reset code
136 * set the cpu to SVC32 mode
143 #define pWDTCTL 0x80001400 /* Watchdog Timer control register */
144 #define pINTENC 0x8000050C /* Interupt-Controller enable clear register */
145 #define pCLKSET 0x80000420 /* clock divisor register */
147 /* disable watchdog, set watchdog control register to
148 * all zeros (default reset)
155 * mask all IRQs by setting all bits in the INTENC register (default)
161 /* FCLK:HCLK:PCLK = 1:2:2 */
162 /* default FCLK is 200 MHz, using 14.7456 MHz fin */
165 @ ldr r1, =0x0005ee39 @ 1: 2: 4
169 * we do sys-critical inits only at reboot,
170 * not when booting from ram!
172 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
176 /* Set stackpointer in internal RAM to call board_init_f */
178 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
182 /*------------------------------------------------------------------------------*/
185 * void relocate_code (addr_sp, gd, addr_moni)
187 * This "function" does not return, instead it continues in RAM
188 * after relocating the monitor code.
193 mov r4, r0 /* save addr_sp */
194 mov r5, r1 /* save addr of gd */
195 mov r6, r2 /* save addr of destination */
196 mov r7, r2 /* save addr of destination */
198 /* Set up the stack */
205 sub r2, r3, r2 /* r2 <- size of armboot */
206 add r2, r0, r2 /* r2 <- source end address */
211 ldmia r0!, {r9-r10} /* copy from source address [r0] */
212 stmia r6!, {r9-r10} /* copy to target address [r1] */
213 cmp r0, r2 /* until source end address [r2] */
216 #ifndef CONFIG_PRELOADER
217 /* fix got entries */
218 ldr r1, _TEXT_BASE /* Text base */
219 mov r0, r7 /* reloc addr */
220 ldr r2, _got_start /* addr in Flash */
221 ldr r3, _got_end /* addr in Flash */
238 #ifndef CONFIG_PRELOADER
241 ldr r3, _TEXT_BASE /* Text base */
242 mov r4, r7 /* reloc addr */
247 mov r2, #0x00000000 /* clear */
249 clbss_l:str r2, [r0] /* clear loop... */
256 * We are done. Do not return, instead branch to second part of board
257 * initialization, now running from RAM.
260 ldr r2, _board_init_r
262 add r2, r2, r7 /* position from board_init_r in RAM */
263 /* setup parameters for board_init_r */
264 mov r0, r5 /* gd_t */
265 mov r1, r7 /* dest_addr */
270 _board_init_r: .word board_init_r
273 *************************************************************************
275 * CPU_init_critical registers
277 * setup important registers
278 * setup memory timing
280 *************************************************************************
286 * flush v4 I/D caches
289 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
290 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
293 * disable MMU stuff and caches
295 mrc p15, 0, r0, c1, c0, 0
296 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
297 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
298 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
299 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
300 orr r0, r0, #0x40000000 @ set bit 30 (nF) notFastBus
301 mcr p15, 0, r0, c1, c0, 0
305 * before relocating, we have to setup RAM timing
306 * because memory timing is board-dependend, you will
307 * find a lowlevel_init.S in your board directory.
317 *************************************************************************
321 *************************************************************************
327 #define S_FRAME_SIZE 72
349 #define MODE_SVC 0x13
353 * use bad_save_user_regs for abort/prefetch/undef/swi ...
354 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
357 .macro bad_save_user_regs
358 sub sp, sp, #S_FRAME_SIZE
359 stmia sp, {r0 - r12} @ Calling r0-r12
360 ldr r2, IRQ_STACK_START_IN
361 ldmia r2, {r2 - r3} @ get pc, cpsr
362 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
366 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
370 .macro irq_save_user_regs
371 sub sp, sp, #S_FRAME_SIZE
372 stmia sp, {r0 - r12} @ Calling r0-r12
374 stmdb r8, {sp, lr}^ @ Calling SP, LR
375 str lr, [r8, #0] @ Save calling PC
377 str r6, [r8, #4] @ Save CPSR
378 str r0, [r8, #8] @ Save OLD_R0
382 .macro irq_restore_user_regs
383 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
385 ldr lr, [sp, #S_PC] @ Get PC
386 add sp, sp, #S_FRAME_SIZE
387 subs pc, lr, #4 @ return & move spsr_svc into cpsr
391 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
393 str lr, [r13] @ save caller lr / spsr
397 mov r13, #MODE_SVC @ prepare SVC-Mode
404 .macro get_irq_stack @ setup IRQ stack
405 ldr sp, IRQ_STACK_START
408 .macro get_fiq_stack @ setup FIQ stack
409 ldr sp, FIQ_STACK_START
416 undefined_instruction:
419 bl do_undefined_instruction
425 bl do_software_interrupt
445 #ifdef CONFIG_USE_IRQ
452 irq_restore_user_regs
457 /* someone ought to write a more effiction fiq_save_user_regs */
460 irq_restore_user_regs
481 bl disable_interrupts
483 /* Disable watchdog */
492 /* Enable the watchdog */