2 * Copyright (C) 2013 Atmel Corporation
3 * Bo Shen <voice.shen@atmel.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/atmel_mpddrc.h>
12 static inline void atmel_mpddr_op(int mode, u32 ram_address)
14 struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
16 writel(mode, &mpddr->mr);
17 writel(0, ram_address);
20 int ddr2_init(const unsigned int ram_address,
21 const struct atmel_mpddr *mpddr_value)
23 struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
26 /* Compute bank offset according to NC in configuration register */
27 ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
28 if (!(mpddr_value->cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
29 ba_off += ((mpddr->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
31 ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
33 /* Program the memory device type into the memory device register */
34 writel(mpddr_value->md, &mpddr->md);
36 /* Program the configuration register */
37 writel(mpddr_value->cr, &mpddr->cr);
39 /* Program the timing register */
40 writel(mpddr_value->tpr0, &mpddr->tpr0);
41 writel(mpddr_value->tpr1, &mpddr->tpr1);
42 writel(mpddr_value->tpr2, &mpddr->tpr2);
44 /* Issue a NOP command */
45 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
47 /* A 200 us is provided to precede any signal toggle */
50 /* Issue a NOP command */
51 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
53 /* Issue an all banks precharge command */
54 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
56 /* Issue an extended mode register set(EMRS2) to choose operation */
57 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
58 ram_address + (0x2 << ba_off));
60 /* Issue an extended mode register set(EMRS3) to set EMSR to 0 */
61 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
62 ram_address + (0x3 << ba_off));
65 * Issue an extended mode register set(EMRS1) to enable DLL and
66 * program D.I.C (output driver impedance control)
68 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
69 ram_address + (0x1 << ba_off));
71 /* Enable DLL reset */
72 cr = readl(&mpddr->cr);
73 writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr);
75 /* A mode register set(MRS) cycle is issued to reset DLL */
76 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
78 /* Issue an all banks precharge command */
79 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
81 /* Two auto-refresh (CBR) cycles are provided */
82 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
83 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
85 /* Disable DLL reset */
86 cr = readl(&mpddr->cr);
87 writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr);
89 /* A mode register set (MRS) cycle is issued to disable DLL reset */
90 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
92 /* Set OCD calibration in default state */
93 cr = readl(&mpddr->cr);
94 writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr);
97 * An extended mode register set (EMRS1) cycle is issued
98 * to OCD default value
100 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
101 ram_address + (0x1 << ba_off));
103 /* OCD calibration mode exit */
104 cr = readl(&mpddr->cr);
105 writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr);
108 * An extended mode register set (EMRS1) cycle is issued
111 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
112 ram_address + (0x1 << ba_off));
114 /* A nornal mode command is provided */
115 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
117 /* Perform a write access to any DDR2-SDRAM address */
118 writel(0, ram_address);
120 /* Write the refresh rate */
121 writel(mpddr_value->rtr, &mpddr->rtr);