2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/hardware.h>
10 #include <asm/arch/sys_proto.h>
13 #define ZYNQ_SILICON_VER_MASK 0xF000
14 #define ZYNQ_SILICON_VER_SHIFT 12
16 DECLARE_GLOBAL_DATA_PTR;
18 static unsigned int zynqmp_get_silicon_version_secure(void)
22 ver = readl(&csu_base->version);
23 ver &= ZYNQMP_SILICON_VER_MASK;
24 ver >>= ZYNQMP_SILICON_VER_SHIFT;
29 unsigned int zynqmp_get_silicon_version(void)
31 if (current_el() == 3)
32 return zynqmp_get_silicon_version_secure();
34 gd->cpu_clk = get_tbclk();
36 switch (gd->cpu_clk) {
38 return ZYNQMP_CSU_VERSION_VELOCE;
40 return ZYNQMP_CSU_VERSION_QEMU;
42 return ZYNQMP_CSU_VERSION_EP108;
45 return ZYNQMP_CSU_VERSION_SILICON;
48 #ifndef CONFIG_SYS_DCACHE_OFF
49 #include <asm/armv8/mmu.h>
51 #define SECTION_SHIFT_L1 30UL
52 #define SECTION_SHIFT_L2 21UL
53 #define BLOCK_SIZE_L0 0x8000000000UL
54 #define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1)
55 #define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2)
57 #define TCR_TG1_4K (1 << 31)
58 #define TCR_EPD1_DISABLE (1 << 23)
59 #define ZYNQMO_VA_BITS 40
60 #define ZYNQMP_TCR TCR_TG1_4K | \
66 TCR_T0SZ(ZYNQMO_VA_BITS)
68 #define MEMORY_ATTR PMD_SECT_AF | PMD_SECT_INNER_SHARE | \
69 PMD_ATTRINDX(MT_NORMAL) | \
71 #define DEVICE_ATTR PMD_SECT_AF | PMD_SECT_PXN | \
72 PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) | \
75 /* 4K size is required to place 512 entries in each level */
76 #define TLB_TABLE_SIZE 0x1000
83 static struct attr_tbl attr_tbll1t0[4] = { {16, 0x0},
88 static struct attr_tbl attr_tbll2t3[4] = { {0x180, DEVICE_ATTR},
95 * This mmu table looks as below
96 * Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0
97 * and other Level1 Table1.
98 * Level1 Table0 contains entries for each 1GB from 0 to 511GB.
99 * Level1 Table1 contains entries for each 1GB from 512GB to 1TB.
100 * Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains
101 * entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively.
103 static void zynqmp_mmu_setup(void)
107 u64 i, section_l1t0, section_l1t1;
108 u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3;
109 u64 *level0_table = (u64 *)gd->arch.tlb_addr;
110 u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE);
111 u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE));
112 u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE));
113 u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE));
114 u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE));
115 u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE));
118 (u64)level1_table_0 | PMD_TYPE_TABLE;
120 (u64)level1_table_1 | PMD_TYPE_TABLE;
123 * set level 1 table 0, covering 0 to 512GB
124 * set level 1 table 1, covering 512GB to 1TB
127 section_l1t1 = BLOCK_SIZE_L0;
130 for (i = 0; i < 512; i++) {
131 level1_table_0[i] = section_l1t0;
132 level1_table_0[i] |= attr_tbll1t0[index_attr].attr;
133 attr_tbll1t0[index_attr].num--;
134 if (attr_tbll1t0[index_attr].num == 0)
136 level1_table_1[i] = section_l1t1;
137 level1_table_1[i] |= DEVICE_ATTR;
138 section_l1t0 += BLOCK_SIZE_L1;
139 section_l1t1 += BLOCK_SIZE_L1;
143 (u64)level2_table_0 | PMD_TYPE_TABLE;
145 (u64)level2_table_1 | PMD_TYPE_TABLE;
147 (u64)level2_table_2 | PMD_TYPE_TABLE;
149 (u64)level2_table_3 | PMD_TYPE_TABLE;
152 section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */
153 section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */
154 section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */
158 for (i = 0; i < 512; i++) {
159 level2_table_0[i] = section_l2t0 | MEMORY_ATTR;
160 level2_table_1[i] = section_l2t1 | MEMORY_ATTR;
161 level2_table_2[i] = section_l2t2 | DEVICE_ATTR;
162 level2_table_3[i] = section_l2t3 |
163 attr_tbll2t3[index_attr].attr;
164 attr_tbll2t3[index_attr].num--;
165 if (attr_tbll2t3[index_attr].num == 0)
167 section_l2t0 += BLOCK_SIZE_L2;
168 section_l2t1 += BLOCK_SIZE_L2;
169 section_l2t2 += BLOCK_SIZE_L2;
170 section_l2t3 += BLOCK_SIZE_L2;
173 /* flush new MMU table */
174 flush_dcache_range(gd->arch.tlb_addr,
175 gd->arch.tlb_addr + gd->arch.tlb_size);
177 /* point TTBR to the new table */
179 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
180 ZYNQMP_TCR, MEMORY_ATTRIBUTES);
182 set_sctlr(get_sctlr() | CR_M);
185 int arch_cpu_init(void)
188 __asm_invalidate_dcache_all();
189 __asm_invalidate_tlb_all();
194 * This function is called from lib/board.c.
195 * It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
196 * There is no need to disable d-cache for this operation.
198 void enable_caches(void)
200 /* The data cache is not active unless the mmu is enabled */
201 if (!(get_sctlr() & CR_M)) {
202 invalidate_dcache_all();
203 __asm_invalidate_tlb_all();
206 puts("Enabling Caches...\n");
208 set_sctlr(get_sctlr() | CR_C);
211 u64 *arch_get_page_table(void)
213 return (u64 *)(gd->arch.tlb_addr + 0x3000);