arch/arm/cpu/armv8/zynqmp/cpu.c

   1 /*
   2  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   3  * Michal Simek <michal.simek@xilinx.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/arch/hardware.h>
  10 #include <asm/arch/sys_proto.h>
  11 #include <asm/io.h>
  12
  13 #define ZYNQ_SILICON_VER_MASK   0xF000
  14 #define ZYNQ_SILICON_VER_SHIFT  12
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 unsigned int zynqmp_get_silicon_version(void)
  19 {
  20         gd->cpu_clk = get_tbclk();
  21
  22         switch (gd->cpu_clk) {
  23         case 50000000:
  24                 return ZYNQMP_CSU_VERSION_QEMU;
  25         }
  26
  27         return ZYNQMP_CSU_VERSION_EP108;
  28 }
  29
  30 #ifndef CONFIG_SYS_DCACHE_OFF
  31 #include <asm/armv8/mmu.h>
  32
  33 #define SECTION_SHIFT_L1        30UL
  34 #define SECTION_SHIFT_L2        21UL
  35 #define BLOCK_SIZE_L0           0x8000000000UL
  36 #define BLOCK_SIZE_L1           (1 << SECTION_SHIFT_L1)
  37 #define BLOCK_SIZE_L2           (1 << SECTION_SHIFT_L2)
  38
  39 #define TCR_TG1_4K              (1 << 31)
  40 #define TCR_EPD1_DISABLE        (1 << 23)
  41 #define ZYNQMO_VA_BITS          40
  42 #define ZYNQMP_TCR              TCR_TG1_4K | \
  43                                 TCR_EPD1_DISABLE | \
  44                                 TCR_SHARED_OUTER | \
  45                                 TCR_SHARED_INNER | \
  46                                 TCR_IRGN_WBWA | \
  47                                 TCR_ORGN_WBWA | \
  48                                 TCR_T0SZ(ZYNQMO_VA_BITS)
  49
  50 #define MEMORY_ATTR     PMD_SECT_AF | PMD_SECT_INNER_SHARE |    \
  51                         PMD_ATTRINDX(MT_NORMAL) |       \
  52                         PMD_TYPE_SECT
  53 #define DEVICE_ATTR     PMD_SECT_AF | PMD_SECT_PXN |    \
  54                         PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) | \
  55                         PMD_TYPE_SECT
  56
  57 /* 4K size is required to place 512 entries in each level */
  58 #define TLB_TABLE_SIZE  0x1000
  59
  60 struct attr_tbl {
  61         u32 num;
  62         u64 attr;
  63 };
  64
  65 static struct attr_tbl attr_tbll1t0[4] = { {16, 0x0},
  66                                            {8, DEVICE_ATTR},
  67                                            {32, MEMORY_ATTR},
  68                                            {456, DEVICE_ATTR}
  69                                          };
  70 static struct attr_tbl attr_tbll2t3[4] = { {0x180, DEVICE_ATTR},
  71                                            {0x40, 0x0},
  72                                            {0x3F, DEVICE_ATTR},
  73                                            {0x1, MEMORY_ATTR}
  74                                          };
  75
  76 /*
  77  * This mmu table looks as below
  78  * Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0
  79  * and other Level1 Table1.
  80  * Level1 Table0 contains entries for each 1GB from 0 to 511GB.
  81  * Level1 Table1 contains entries for each 1GB from 512GB to 1TB.
  82  * Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains
  83  * entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively.
  84  */
  85 static void zynqmp_mmu_setup(void)
  86 {
  87         int el;
  88         u32 index_attr;
  89         u64 i, section_l1t0, section_l1t1;
  90         u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3;
  91         u64 *level0_table = (u64 *)gd->arch.tlb_addr;
  92         u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE);
  93         u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE));
  94         u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE));
  95         u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE));
  96         u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE));
  97         u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE));
  98
  99         level0_table[0] =
 100                 (u64)level1_table_0 | PMD_TYPE_TABLE;
 101         level0_table[1] =
 102                 (u64)level1_table_1 | PMD_TYPE_TABLE;
 103
 104         /*
 105          * set level 1 table 0, covering 0 to 512GB
 106          * set level 1 table 1, covering 512GB to 1TB
 107          */
 108         section_l1t0 = 0;
 109         section_l1t1 = BLOCK_SIZE_L0;
 110
 111         index_attr = 0;
 112         for (i = 0; i < 512; i++) {
 113                 level1_table_0[i] = section_l1t0;
 114                 level1_table_0[i] |= attr_tbll1t0[index_attr].attr;
 115                 attr_tbll1t0[index_attr].num--;
 116                 if (attr_tbll1t0[index_attr].num == 0)
 117                         index_attr++;
 118                 level1_table_1[i] = section_l1t1;
 119                 level1_table_1[i] |= DEVICE_ATTR;
 120                 section_l1t0 += BLOCK_SIZE_L1;
 121                 section_l1t1 += BLOCK_SIZE_L1;
 122         }
 123
 124         level1_table_0[0] =
 125                 (u64)level2_table_0 | PMD_TYPE_TABLE;
 126         level1_table_0[1] =
 127                 (u64)level2_table_1 | PMD_TYPE_TABLE;
 128         level1_table_0[2] =
 129                 (u64)level2_table_2 | PMD_TYPE_TABLE;
 130         level1_table_0[3] =
 131                 (u64)level2_table_3 | PMD_TYPE_TABLE;
 132
 133         section_l2t0 = 0;
 134         section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */
 135         section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */
 136         section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */
 137
 138         index_attr = 0;
 139
 140         for (i = 0; i < 512; i++) {
 141                 level2_table_0[i] = section_l2t0 | MEMORY_ATTR;
 142                 level2_table_1[i] = section_l2t1 | MEMORY_ATTR;
 143                 level2_table_2[i] = section_l2t2 | DEVICE_ATTR;
 144                 level2_table_3[i] = section_l2t3 |
 145                                     attr_tbll2t3[index_attr].attr;
 146                 attr_tbll2t3[index_attr].num--;
 147                 if (attr_tbll2t3[index_attr].num == 0)
 148                         index_attr++;
 149                 section_l2t0 += BLOCK_SIZE_L2;
 150                 section_l2t1 += BLOCK_SIZE_L2;
 151                 section_l2t2 += BLOCK_SIZE_L2;
 152                 section_l2t3 += BLOCK_SIZE_L2;
 153         }
 154
 155         /* flush new MMU table */
 156         flush_dcache_range(gd->arch.tlb_addr,
 157                            gd->arch.tlb_addr + gd->arch.tlb_size);
 158
 159         /* point TTBR to the new table */
 160         el = current_el();
 161         set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
 162                           ZYNQMP_TCR, MEMORY_ATTRIBUTES);
 163
 164         set_sctlr(get_sctlr() | CR_M);
 165 }
 166
 167 int arch_cpu_init(void)
 168 {
 169         icache_enable();
 170         __asm_invalidate_dcache_all();
 171         __asm_invalidate_tlb_all();
 172         return 0;
 173 }
 174
 175 /*
 176  * This function is called from lib/board.c.
 177  * It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
 178  * There is no need to disable d-cache for this operation.
 179  */
 180 void enable_caches(void)
 181 {
 182         /* The data cache is not active unless the mmu is enabled */
 183         if (!(get_sctlr() & CR_M)) {
 184                 invalidate_dcache_all();
 185                 __asm_invalidate_tlb_all();
 186                 zynqmp_mmu_setup();
 187         }
 188         puts("Enabling Caches...\n");
 189
 190         set_sctlr(get_sctlr() | CR_C);
 191 }
 192 #endif