1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
8 #include <asm/arch/clk.h>
9 #include <asm/arch/hardware.h>
10 #include <asm/arch/sys_proto.h>
12 DECLARE_GLOBAL_DATA_PTR;
14 unsigned long zynqmp_get_system_timer_freq(void)
16 u32 ver = zynqmp_get_silicon_version();
19 case ZYNQMP_CSU_VERSION_VELOCE:
21 case ZYNQMP_CSU_VERSION_EP108:
23 case ZYNQMP_CSU_VERSION_QEMU:
32 * set_cpu_clk_info() - Initialize clock framework
33 * Always returns zero.
35 * This function is called from common code after relocation and sets up the
36 * clock framework. The framework must not be used before this function had been
39 int set_cpu_clk_info(void)
41 gd->cpu_clk = get_tbclk();
43 /* Support Veloce to show at least 1MHz via bdi */
44 if (gd->cpu_clk > 1000000)
45 gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
47 gd->bd->bi_arm_freq = 1;
49 gd->bd->bi_dsp_freq = 0;