3 * David Feng <fenghua@phytium.com.cn>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm-offsets.h>
10 #include <linux/linkage.h>
11 #include <asm/macro.h>
12 #include <asm/armv8/mmu.h>
14 /*************************************************************************
16 * Startup Code (reset vector)
18 *************************************************************************/
22 #if defined(LINUX_KERNEL_IMAGE_HEADER)
23 #include <asm/boot0-linux-kernel-header.h>
24 #elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
26 * Various SoCs need something special and SoC-specific up front in
27 * order to boot, allow them to set that in their boot0.h file and then
30 #include <asm/arch/boot0.h>
39 .quad CONFIG_SYS_TEXT_BASE
42 * These are defined in the linker script.
50 .quad __bss_start - _start
54 .quad __bss_end - _start
57 /* Allow the board to save important registers */
59 .globl save_boot_params_ret
62 #if CONFIG_POSITION_INDEPENDENT
64 * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
65 * executed at a different address than it was linked at.
68 adr x0, _start /* x0 <- Runtime value of _start */
69 ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */
70 sub x9, x0, x1 /* x9 <- Run-vs-link offset */
71 adr x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */
72 adr x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */
74 ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */
75 ldr x4, [x2], #8 /* x4 <- addend */
76 cmp w1, #1027 /* relative fixup? */
78 /* relative fix: store addend plus offset at dest location */
88 #ifdef CONFIG_SYS_RESET_SCTRL
92 * Could be EL3/EL2/EL1, Initial State:
93 * Little Endian, MMU Disabled, i/dCache Disabled
96 switch_el x1, 3f, 2f, 1f
99 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
101 msr cptr_el3, xzr /* Enable FP/SIMD */
102 #ifdef COUNTER_FREQUENCY
103 ldr x0, =COUNTER_FREQUENCY
104 msr cntfrq_el0, x0 /* Initialize CNTFRQ */
109 msr cptr_el2, x0 /* Enable FP/SIMD */
113 msr cpacr_el1, x0 /* Enable FP/SIMD */
117 * Enable SMPEN bit for coherency.
118 * This register is not architectural but at the moment
119 * this bit should be set for A53/A57/A72.
121 #ifdef CONFIG_ARMV8_SET_SMPEN
122 switch_el x1, 3f, 1f, 1f
124 mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */
126 msr S3_1_c15_c2_1, x0
130 /* Apply ARM core specific erratas */
134 * Cache/BPB/TLB Invalidate
135 * i-cache is invalidated before enabled in icache_enable()
136 * tlb is invalidated before mmu is enabled in dcache_enable()
137 * d-cache is invalidated before enabled in dcache_enable()
140 /* Processor specific initialization */
143 #if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
144 branch_if_master x0, x1, master_cpu
145 b spin_table_secondary_jump
147 #elif defined(CONFIG_ARMV8_MULTIENTRY)
148 branch_if_master x0, x1, master_cpu
155 ldr x1, =CPU_RELEASE_ADDR
158 br x0 /* branch to the given address */
159 #endif /* CONFIG_ARMV8_MULTIENTRY */
163 #ifdef CONFIG_SYS_RESET_SCTRL
165 switch_el x1, 3f, 2f, 1f
179 switch_el x1, 6f, 5f, 4f
192 b __asm_invalidate_tlb_all
196 /*-----------------------------------------------------------------------*/
198 WEAK(apply_core_errata)
200 mov x29, lr /* Save LR */
201 /* For now, we support Cortex-A53, Cortex-A57 specific errata */
203 /* Check if we are running on a Cortex-A53 core */
204 branch_if_a53_core x0, apply_a53_core_errata
206 /* Check if we are running on a Cortex-A57 core */
207 branch_if_a57_core x0, apply_a57_core_errata
209 mov lr, x29 /* Restore LR */
212 apply_a53_core_errata:
214 #ifdef CONFIG_ARM_ERRATA_855873
224 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
225 /* Enable data cache clean as data cache clean/invalidate */
227 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
231 apply_a57_core_errata:
233 #ifdef CONFIG_ARM_ERRATA_828024
234 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
235 /* Disable non-allocate hint of w-b-n-a memory type */
237 /* Disable write streaming no L1-allocate threshold */
239 /* Disable write streaming no-allocate threshold */
241 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
244 #ifdef CONFIG_ARM_ERRATA_826974
245 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
246 /* Disable speculative load execution ahead of a DMB */
248 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
251 #ifdef CONFIG_ARM_ERRATA_833471
252 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
253 /* FPSCR write flush.
254 * Note that in some cases where a flush is unnecessary this
255 could impact performance. */
257 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
260 #ifdef CONFIG_ARM_ERRATA_829520
261 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
262 /* Disable Indirect Predictor bit will prevent this erratum
264 * Note that in some cases where a flush is unnecessary this
265 could impact performance. */
267 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
270 #ifdef CONFIG_ARM_ERRATA_833069
271 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
272 /* Disable Enable Invalidates of BTB bit */
274 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
277 ENDPROC(apply_core_errata)
279 /*-----------------------------------------------------------------------*/
282 mov x29, lr /* Save LR */
284 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
285 branch_if_slave x0, 1f
289 #if defined(CONFIG_GICV3)
291 bl gic_init_secure_percpu
292 #elif defined(CONFIG_GICV2)
295 bl gic_init_secure_percpu
299 #ifdef CONFIG_ARMV8_MULTIENTRY
300 branch_if_master x0, x1, 2f
303 * Slave should wait for master clearing spin table.
304 * This sync prevent salves observing incorrect
305 * value of spin table and jumping to wrong place.
307 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
311 bl gic_wait_for_interrupt
315 * All slaves will enter EL2 and optionally EL1.
317 adr x4, lowlevel_in_el2
318 ldr x5, =ES_TO_AARCH64
319 bl armv8_switch_to_el2
322 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
323 adr x4, lowlevel_in_el1
324 ldr x5, =ES_TO_AARCH64
325 bl armv8_switch_to_el1
330 #endif /* CONFIG_ARMV8_MULTIENTRY */
333 mov lr, x29 /* Restore LR */
335 ENDPROC(lowlevel_init)
337 WEAK(smp_kick_all_cpus)
338 /* Kick secondary cpus up by SGI 0 interrupt */
339 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
341 b gic_kick_secondary_cpus
344 ENDPROC(smp_kick_all_cpus)
346 /*-----------------------------------------------------------------------*/
348 ENTRY(c_runtime_cpu_setup)
351 switch_el x1, 3f, 2f, 1f
360 ENDPROC(c_runtime_cpu_setup)
362 WEAK(save_boot_params)
363 b save_boot_params_ret /* back to my caller */
364 ENDPROC(save_boot_params)