1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * David Feng <fenghua@phytium.com.cn>
7 #include <asm-offsets.h>
9 #include <linux/linkage.h>
10 #include <asm/macro.h>
11 #include <asm/armv8/mmu.h>
13 /*************************************************************************
15 * Startup Code (reset vector)
17 *************************************************************************/
21 #if defined(LINUX_KERNEL_IMAGE_HEADER)
22 #include <asm/boot0-linux-kernel-header.h>
23 #elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
25 * Various SoCs need something special and SoC-specific up front in
26 * order to boot, allow them to set that in their boot0.h file and then
29 #ifdef CONFIG_ARCH_ROCKCHIP
30 #include <asm/arch-rockchip/boot0.h>
32 #include <asm/arch/boot0.h>
42 .quad CONFIG_SYS_TEXT_BASE
45 * These are defined in the linker script.
53 .quad __bss_start - _start
57 .quad __bss_end - _start
60 /* Allow the board to save important registers */
62 .globl save_boot_params_ret
65 #if CONFIG_POSITION_INDEPENDENT
67 * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
68 * executed at a different address than it was linked at.
71 adr x0, _start /* x0 <- Runtime value of _start */
72 ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */
73 sub x9, x0, x1 /* x9 <- Run-vs-link offset */
74 adr x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */
75 adr x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */
77 ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */
78 ldr x4, [x2], #8 /* x4 <- addend */
79 cmp w1, #1027 /* relative fixup? */
81 /* relative fix: store addend plus offset at dest location */
91 #ifdef CONFIG_SYS_RESET_SCTRL
95 #if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
96 .macro set_vbar, regname, reg
101 .macro set_vbar, regname, reg
105 * Could be EL3/EL2/EL1, Initial State:
106 * Little Endian, MMU Disabled, i/dCache Disabled
108 switch_el x1, 3f, 2f, 1f
109 3: set_vbar vbar_el3, x0
111 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
113 msr cptr_el3, xzr /* Enable FP/SIMD */
114 #ifdef COUNTER_FREQUENCY
115 ldr x0, =COUNTER_FREQUENCY
116 msr cntfrq_el0, x0 /* Initialize CNTFRQ */
119 2: set_vbar vbar_el2, x0
121 msr cptr_el2, x0 /* Enable FP/SIMD */
123 1: set_vbar vbar_el1, x0
125 msr cpacr_el1, x0 /* Enable FP/SIMD */
129 * Enable SMPEN bit for coherency.
130 * This register is not architectural but at the moment
131 * this bit should be set for A53/A57/A72.
133 #ifdef CONFIG_ARMV8_SET_SMPEN
134 switch_el x1, 3f, 1f, 1f
136 mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */
138 msr S3_1_c15_c2_1, x0
142 /* Apply ARM core specific erratas */
146 * Cache/BPB/TLB Invalidate
147 * i-cache is invalidated before enabled in icache_enable()
148 * tlb is invalidated before mmu is enabled in dcache_enable()
149 * d-cache is invalidated before enabled in dcache_enable()
152 /* Processor specific initialization */
155 #if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
156 branch_if_master x0, x1, master_cpu
157 b spin_table_secondary_jump
159 #elif defined(CONFIG_ARMV8_MULTIENTRY)
160 branch_if_master x0, x1, master_cpu
167 ldr x1, =CPU_RELEASE_ADDR
170 br x0 /* branch to the given address */
171 #endif /* CONFIG_ARMV8_MULTIENTRY */
175 #ifdef CONFIG_SYS_RESET_SCTRL
177 switch_el x1, 3f, 2f, 1f
191 switch_el x1, 6f, 5f, 4f
204 b __asm_invalidate_tlb_all
208 /*-----------------------------------------------------------------------*/
210 WEAK(apply_core_errata)
212 mov x29, lr /* Save LR */
213 /* For now, we support Cortex-A53, Cortex-A57 specific errata */
215 /* Check if we are running on a Cortex-A53 core */
216 branch_if_a53_core x0, apply_a53_core_errata
218 /* Check if we are running on a Cortex-A57 core */
219 branch_if_a57_core x0, apply_a57_core_errata
221 mov lr, x29 /* Restore LR */
224 apply_a53_core_errata:
226 #ifdef CONFIG_ARM_ERRATA_855873
236 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
237 /* Enable data cache clean as data cache clean/invalidate */
239 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
243 apply_a57_core_errata:
245 #ifdef CONFIG_ARM_ERRATA_828024
246 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
247 /* Disable non-allocate hint of w-b-n-a memory type */
249 /* Disable write streaming no L1-allocate threshold */
251 /* Disable write streaming no-allocate threshold */
253 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
256 #ifdef CONFIG_ARM_ERRATA_826974
257 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
258 /* Disable speculative load execution ahead of a DMB */
260 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
263 #ifdef CONFIG_ARM_ERRATA_833471
264 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
265 /* FPSCR write flush.
266 * Note that in some cases where a flush is unnecessary this
267 could impact performance. */
269 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
272 #ifdef CONFIG_ARM_ERRATA_829520
273 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
274 /* Disable Indirect Predictor bit will prevent this erratum
276 * Note that in some cases where a flush is unnecessary this
277 could impact performance. */
279 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
282 #ifdef CONFIG_ARM_ERRATA_833069
283 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
284 /* Disable Enable Invalidates of BTB bit */
286 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
289 ENDPROC(apply_core_errata)
291 /*-----------------------------------------------------------------------*/
294 mov x29, lr /* Save LR */
296 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
297 branch_if_slave x0, 1f
301 #if defined(CONFIG_GICV3)
303 bl gic_init_secure_percpu
304 #elif defined(CONFIG_GICV2)
307 bl gic_init_secure_percpu
311 #ifdef CONFIG_ARMV8_MULTIENTRY
312 branch_if_master x0, x1, 2f
315 * Slave should wait for master clearing spin table.
316 * This sync prevent salves observing incorrect
317 * value of spin table and jumping to wrong place.
319 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
323 bl gic_wait_for_interrupt
327 * All slaves will enter EL2 and optionally EL1.
329 adr x4, lowlevel_in_el2
330 ldr x5, =ES_TO_AARCH64
331 bl armv8_switch_to_el2
334 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
335 adr x4, lowlevel_in_el1
336 ldr x5, =ES_TO_AARCH64
337 bl armv8_switch_to_el1
342 #endif /* CONFIG_ARMV8_MULTIENTRY */
345 mov lr, x29 /* Restore LR */
347 ENDPROC(lowlevel_init)
349 WEAK(smp_kick_all_cpus)
350 /* Kick secondary cpus up by SGI 0 interrupt */
351 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
353 b gic_kick_secondary_cpus
356 ENDPROC(smp_kick_all_cpus)
358 /*-----------------------------------------------------------------------*/
360 ENTRY(c_runtime_cpu_setup)
361 #if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
364 switch_el x1, 3f, 2f, 1f
374 ENDPROC(c_runtime_cpu_setup)
376 WEAK(save_boot_params)
377 b save_boot_params_ret /* back to my caller */
378 ENDPROC(save_boot_params)