2 * Copyright (C) 2015 Linaro.
3 * Peter Griffin <peter.griffin@linaro.org>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/pinmux.h>
14 struct hi6220_pinmux0_regs *pmx0 =
15 (struct hi6220_pinmux0_regs *)HI6220_PINMUX0_BASE;
17 struct hi6220_pinmux1_regs *pmx1 =
18 (struct hi6220_pinmux1_regs *)HI6220_PINMUX1_BASE;
20 static void hi6220_uart_config(int peripheral)
24 writel(MUX_M0, &pmx0->iomg[48]); /* UART0_RXD */
25 writel(MUX_M0, &pmx0->iomg[49]); /* UART0_TXD */
27 writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[49]); /* UART0_RXD */
28 writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[50]); /* UART0_TXD */
32 writel(MUX_M0, &pmx0->iomg[50]); /* UART1_CTS_N */
33 writel(MUX_M0, &pmx0->iomg[51]); /* UART1_RTS_N */
34 writel(MUX_M0, &pmx0->iomg[52]); /* UART1_RXD */
35 writel(MUX_M0, &pmx0->iomg[53]); /* UART1_TXD */
37 writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[51]); /*UART1_CTS_N*/
38 writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[53]); /* UART1_RXD */
39 writel(DRIVE1_02MA, &pmx1->iocfg[52]); /* UART1_RTS_N */
40 writel(DRIVE1_02MA, &pmx1->iocfg[54]); /* UART1_TXD */
44 writel(MUX_M0, &pmx0->iomg[54]); /* UART2_CTS_N */
45 writel(MUX_M0, &pmx0->iomg[55]); /* UART2_RTS_N */
46 writel(MUX_M0, &pmx0->iomg[56]); /* UART2_RXD */
47 writel(MUX_M0, &pmx0->iomg[57]); /* UART2_TXD */
49 writel(DRIVE1_02MA, &pmx1->iocfg[55]); /* UART2_CTS_N */
50 writel(DRIVE1_02MA, &pmx1->iocfg[56]); /* UART2_RTS_N */
51 writel(DRIVE1_02MA, &pmx1->iocfg[57]); /* UART2_RXD */
52 writel(DRIVE1_02MA, &pmx1->iocfg[58]); /* UART2_TXD */
56 writel(MUX_M1, &pmx0->iomg[96]); /* UART3_CTS_N */
57 writel(MUX_M1, &pmx0->iomg[97]); /* UART3_RTS_N */
58 writel(MUX_M1, &pmx0->iomg[98]); /* UART3_RXD */
59 writel(MUX_M1, &pmx0->iomg[99]); /* UART3_TXD */
62 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[100]);
64 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[101]);
66 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[102]);
68 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[103]);
72 writel(MUX_M1, &pmx0->iomg[116]); /* UART4_CTS_N */
73 writel(MUX_M1, &pmx0->iomg[117]); /* UART4_RTS_N */
74 writel(MUX_M1, &pmx0->iomg[118]); /* UART4_RXD */
75 writel(MUX_M1, &pmx0->iomg[119]); /* UART4_TXD */
78 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[120]);
80 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[121]);
82 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[122]);
84 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[123]);
87 writel(MUX_M1, &pmx0->iomg[114]); /* UART5_RXD */
88 writel(MUX_M1, &pmx0->iomg[115]); /* UART5_TXD */
91 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[118]);
93 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[119]);
98 debug("%s: invalid peripheral %d", __func__, peripheral);
103 static int hi6220_mmc_config(int peripheral)
107 switch (peripheral) {
108 case PERIPH_ID_SDMMC0:
110 /* eMMC pinmux config */
111 writel(MUX_M0, &pmx0->iomg[64]); /* EMMC_CLK */
112 writel(MUX_M0, &pmx0->iomg[65]); /* EMMC_CMD */
113 writel(MUX_M0, &pmx0->iomg[66]); /* EMMC_DATA0 */
114 writel(MUX_M0, &pmx0->iomg[67]); /* EMMC_DATA1 */
115 writel(MUX_M0, &pmx0->iomg[68]); /* EMMC_DATA2 */
116 writel(MUX_M0, &pmx0->iomg[69]); /* EMMC_DATA3 */
117 writel(MUX_M0, &pmx0->iomg[70]); /* EMMC_DATA4 */
118 writel(MUX_M0, &pmx0->iomg[71]); /* EMMC_DATA5 */
119 writel(MUX_M0, &pmx0->iomg[72]); /* EMMC_DATA6 */
120 writel(MUX_M0, &pmx0->iomg[73]); /* EMMC_DATA7 */
122 /*eMMC configure up/down/drive */
123 writel(DRIVE1_08MA, &pmx1->iocfg[65]); /* EMMC_CLK */
125 tmp = DRIVE1_04MA | PULL_UP;
126 writel(tmp, &pmx1->iocfg[65]); /* EMMC_CMD */
127 writel(tmp, &pmx1->iocfg[66]); /* EMMC_DATA0 */
128 writel(tmp, &pmx1->iocfg[67]); /* EMMC_DATA1 */
129 writel(tmp, &pmx1->iocfg[68]); /* EMMC_DATA2 */
130 writel(tmp, &pmx1->iocfg[69]); /* EMMC_DATA3 */
131 writel(tmp, &pmx1->iocfg[70]); /* EMMC_DATA4 */
132 writel(tmp, &pmx1->iocfg[71]); /* EMMC_DATA5 */
133 writel(tmp, &pmx1->iocfg[72]); /* EMMC_DATA6 */
134 writel(tmp, &pmx1->iocfg[73]); /* EMMC_DATA7 */
136 writel(DRIVE1_04MA, &pmx1->iocfg[73]); /* EMMC_RST_N */
139 case PERIPH_ID_SDMMC1:
141 writel(MUX_M0, &pmx0->iomg[3]); /* SD_CLK */
142 writel(MUX_M0, &pmx0->iomg[4]); /* SD_CMD */
143 writel(MUX_M0, &pmx0->iomg[5]); /* SD_DATA0 */
144 writel(MUX_M0, &pmx0->iomg[6]); /* SD_DATA1 */
145 writel(MUX_M0, &pmx0->iomg[7]); /* SD_DATA2 */
146 writel(MUX_M0, &pmx0->iomg[8]); /* SD_DATA3 */
148 writel(DRIVE1_10MA | BIT(2), &pmx1->iocfg[3]); /*SD_CLK*/
149 writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[4]); /*SD_CMD*/
150 writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[5]); /*SD_DATA0*/
151 writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[6]); /*SD_DATA1*/
152 writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[7]); /*SD_DATA2*/
153 writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[8]); /*SD_DATA3*/
157 debug("%s: invalid peripheral %d", __func__, peripheral);
164 int hi6220_pinmux_config(int peripheral)
166 switch (peripheral) {
167 case PERIPH_ID_UART0:
168 case PERIPH_ID_UART1:
169 case PERIPH_ID_UART2:
170 case PERIPH_ID_UART3:
171 hi6220_uart_config(peripheral);
173 case PERIPH_ID_SDMMC0:
174 case PERIPH_ID_SDMMC1:
175 return hi6220_mmc_config(peripheral);
177 debug("%s: invalid peripheral %d", __func__, peripheral);