2 * GIC Initialization Routines.
5 * David Feng <fenghua@phytium.com.cn>
7 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm-offsets.h>
12 #include <linux/linkage.h>
13 #include <asm/macro.h>
17 /*************************************************************************
19 * void gic_init(void) __attribute__((weak));
21 * Currently, this routine only initialize secure copy of GIC
22 * with Security Extensions at EL3.
24 *************************************************************************/
26 branch_if_slave x0, 2f
28 /* Initialize Distributor and SPIs */
30 mov w0, #0x3 /* EnableGrp0 | EnableGrp1 */
31 str w0, [x1, GICD_CTLR] /* Secure GICD_CTLR */
32 ldr w0, [x1, GICD_TYPER]
33 and w2, w0, #0x1f /* ITLinesNumber */
34 cbz w2, 2f /* No SPIs */
35 add x1, x1, (GICD_IGROUPRn + 4)
36 mov w0, #~0 /* Config SPIs as Grp1 */
41 /* Initialize SGIs and PPIs */
43 mov w0, #~0 /* Config SGIs and PPIs as Grp1 */
44 str w0, [x1, GICD_IGROUPRn] /* GICD_IGROUPR0 */
45 mov w0, #0x1 /* Enable SGI 0 */
46 str w0, [x1, GICD_ISENABLERn]
48 /* Initialize Cpu Interface */
50 mov w0, #0x1e7 /* Disable IRQ/FIQ Bypass & */
51 /* Enable Ack Group1 Interrupt & */
52 /* EnableGrp0 & EnableGrp1 */
53 str w0, [x1, GICC_CTLR] /* Secure GICC_CTLR */
55 mov w0, #0x1 << 7 /* Non-Secure access to GICC_PMR */
56 str w0, [x1, GICC_PMR]
62 /*************************************************************************
64 * void gic_send_sgi(u64 sgi) __attribute__((weak));
66 *************************************************************************/
70 movk w2, #0x100, lsl #16
72 str w2, [x1, GICD_SGIR]
77 /*************************************************************************
79 * void wait_for_wakeup(void) __attribute__((weak));
81 * Wait for SGI 0 from master.
83 *************************************************************************/
87 ldr w0, [x1, GICC_AIAR]
88 str w0, [x1, GICC_AEOIR]
91 ENDPROC(wait_for_wakeup)
94 /*************************************************************************
96 * void smp_kick_all_cpus(void) __attribute__((weak));
98 *************************************************************************/
99 WEAK(smp_kick_all_cpus)
100 /* Kick secondary cpus up by SGI 0 interrupt */
101 mov x0, xzr /* SGI 0 */
102 mov x29, lr /* Save LR */
104 mov lr, x29 /* Restore LR */
106 ENDPROC(smp_kick_all_cpus)