2 * Copyright 2014-2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/soc.h>
13 #include <asm/global_data.h>
14 #include <asm/arch-fsl-layerscape/config.h>
15 #include <fsl_ddr_sdram.h>
17 #ifdef CONFIG_CHAIN_OF_TRUST
18 #include <fsl_validate.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 bool soc_has_dp_ddr(void)
25 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
26 u32 svr = gur_in32(&gur->svr);
28 /* LS2085A has DP_DDR */
29 if (SVR_SOC_VER(svr) == SVR_LS2085)
35 bool soc_has_aiop(void)
37 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
38 u32 svr = gur_in32(&gur->svr);
40 /* LS2085A has AIOP */
41 if (SVR_SOC_VER(svr) == SVR_LS2085)
49 * This erratum requires setting a value to eddrtqcr1 to
50 * optimal the DDR performance.
52 static void erratum_a008336(void)
56 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
57 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
58 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
59 out_le32(eddrtqcr1, 0x63b30002);
61 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
62 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
63 out_le32(eddrtqcr1, 0x63b30002);
69 * This erratum requires a register write before being Memory
70 * controller 3 being enabled.
72 static void erratum_a008514(void)
76 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
77 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
78 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
79 out_le32(eddrtqcr1, 0x63b20002);
83 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
84 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
86 static unsigned long get_internval_val_mhz(void)
88 char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
90 * interval is the number of platform cycles(MHz) between
91 * wake up events generated by EPU.
93 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
96 interval_mhz = simple_strtoul(interval, NULL, 10);
101 void erratum_a009635(void)
104 unsigned long interval_mhz = get_internval_val_mhz();
109 val = in_le32(DCSR_CGACRE5);
110 writel(val | 0x00000200, DCSR_CGACRE5);
112 val = in_le32(EPU_EPCMPR5);
113 writel(interval_mhz, EPU_EPCMPR5);
114 val = in_le32(EPU_EPCCR5);
115 writel(val | 0x82820000, EPU_EPCCR5);
116 val = in_le32(EPU_EPSMCR5);
117 writel(val | 0x002f0000, EPU_EPSMCR5);
118 val = in_le32(EPU_EPECR5);
119 writel(val | 0x20000000, EPU_EPECR5);
120 val = in_le32(EPU_EPGCR);
121 writel(val | 0x80000000, EPU_EPGCR);
123 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
125 static void erratum_a008751(void)
127 #ifdef CONFIG_SYS_FSL_ERRATUM_A008751
128 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
130 writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4);
134 static void erratum_rcw_src(void)
136 #if defined(CONFIG_SPL)
137 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
138 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
141 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
142 val &= ~DCFG_PORSR1_RCW_SRC;
143 val |= DCFG_PORSR1_RCW_SRC_NOR;
144 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
148 #define I2C_DEBUG_REG 0x6
149 #define I2C_GLITCH_EN 0x8
151 * This erratum requires setting glitch_en bit to enable
152 * digital glitch filter to improve clock stability.
154 static void erratum_a009203(void)
157 #ifdef CONFIG_SYS_I2C
158 #ifdef I2C1_BASE_ADDR
159 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
161 writeb(I2C_GLITCH_EN, ptr);
163 #ifdef I2C2_BASE_ADDR
164 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
166 writeb(I2C_GLITCH_EN, ptr);
168 #ifdef I2C3_BASE_ADDR
169 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
171 writeb(I2C_GLITCH_EN, ptr);
173 #ifdef I2C4_BASE_ADDR
174 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
176 writeb(I2C_GLITCH_EN, ptr);
180 void bypass_smmu(void)
183 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
184 out_le32(SMMU_SCR0, val);
185 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
186 out_le32(SMMU_NSCR0, val);
188 void fsl_lsch3_early_init_f(void)
192 init_early_memctl_regs(); /* tighten IFC timing */
196 #ifdef CONFIG_CHAIN_OF_TRUST
197 /* In case of Secure Boot, the IBR configures the SMMU
198 * to allow only Secure transactions.
199 * SMMU must be reset in bypass mode.
200 * Set the ClientPD bit and Clear the USFCFG Bit
202 if (fsl_check_boot_mode_secure() == 1)
207 #ifdef CONFIG_SCSI_AHCI_PLAT
210 struct ccsr_ahci __iomem *ccsr_ahci;
212 ccsr_ahci = (void *)CONFIG_SYS_SATA2;
213 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
214 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
216 ccsr_ahci = (void *)CONFIG_SYS_SATA1;
217 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
218 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
220 ahci_init((void __iomem *)CONFIG_SYS_SATA1);
227 #elif defined(CONFIG_FSL_LSCH2)
228 #ifdef CONFIG_SCSI_AHCI_PLAT
231 struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
233 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
234 out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
235 out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
236 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
238 ahci_init((void __iomem *)CONFIG_SYS_SATA);
245 static void erratum_a009929(void)
247 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
248 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
249 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
250 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
252 rstrqmr1 |= 0x00000400;
253 gur_out32(&gur->rstrqmr1, rstrqmr1);
254 writel(0x01000000, dcsr_cop_ccp);
259 * This erratum requires setting a value to eddrtqcr1 to optimal
260 * the DDR performance. The eddrtqcr1 register is in SCFG space
261 * of LS1043A and the offset is 0x157_020c.
263 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
264 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
265 #error A009660 and A008514 can not be both enabled.
268 static void erratum_a009660(void)
270 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
271 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
272 out_be32(eddrtqcr1, 0x63b20042);
276 static void erratum_a008850_early(void)
278 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
280 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
281 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
283 /* disables propagation of barrier transactions to DDRC from CCI400 */
284 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
286 /* disable the re-ordering in DDRC */
287 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
291 void erratum_a008850_post(void)
293 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
295 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
296 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
299 /* enable propagation of barrier transactions to DDRC from CCI400 */
300 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
302 /* enable the re-ordering in DDRC */
303 tmp = ddr_in32(&ddr->eor);
304 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
305 ddr_out32(&ddr->eor, tmp);
309 void fsl_lsch2_early_init_f(void)
311 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
312 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
314 #ifdef CONFIG_FSL_IFC
315 init_early_memctl_regs(); /* tighten IFC timing */
318 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
319 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
321 /* Make SEC reads and writes snoopable */
322 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
323 SCFG_SNPCNFGCR_SECWRSNP);
326 * Enable snoop requests and DVM message requests for
327 * Slave insterface S4 (A53 core cluster)
329 out_le32(&cci->slave[4].snoop_ctrl,
330 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
333 erratum_a008850_early(); /* part 1 of 2 */
339 #ifdef CONFIG_BOARD_LATE_INIT
340 int board_late_init(void)
342 #ifdef CONFIG_SCSI_AHCI_PLAT
345 #ifdef CONFIG_CHAIN_OF_TRUST
346 fsl_setenv_chain_of_trust();