2 * Copyright 2014-2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/soc.h>
15 #include <asm/global_data.h>
16 #include <asm/arch-fsl-layerscape/config.h>
17 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
20 #ifdef CONFIG_SYS_FSL_DDR
21 #include <fsl_ddr_sdram.h>
24 #ifdef CONFIG_CHAIN_OF_TRUST
25 #include <fsl_validate.h>
27 #include <fsl_immap.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 bool soc_has_dp_ddr(void)
33 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
34 u32 svr = gur_in32(&gur->svr);
36 /* LS2085A, LS2088A, LS2048A has DP_DDR */
37 if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
38 (SVR_SOC_VER(svr) == SVR_LS2088A) ||
39 (SVR_SOC_VER(svr) == SVR_LS2048A))
45 bool soc_has_aiop(void)
47 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
48 u32 svr = gur_in32(&gur->svr);
50 /* LS2085A has AIOP */
51 if (SVR_SOC_VER(svr) == SVR_LS2085A)
57 static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
59 scfg_clrsetbits32(scfg + offset / 4,
61 SCFG_USB_TXVREFTUNE << 6);
64 static void erratum_a009008(void)
66 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
67 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
69 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
70 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
71 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
72 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
73 #elif defined(CONFIG_ARCH_LS2080A)
74 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
76 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
79 static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
81 scfg_clrbits32(scfg + offset / 4,
82 SCFG_USB_SQRXTUNE_MASK << 23);
85 static void erratum_a009798(void)
87 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
88 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
90 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
91 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
92 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
93 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
94 #elif defined(CONFIG_ARCH_LS2080A)
95 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
97 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
100 #if defined(CONFIG_FSL_LSCH3)
102 * This erratum requires setting a value to eddrtqcr1 to
103 * optimal the DDR performance.
105 static void erratum_a008336(void)
107 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
110 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
111 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
112 if (fsl_ddr_get_version(0) == 0x50200)
113 out_le32(eddrtqcr1, 0x63b30002);
115 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
116 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
117 if (fsl_ddr_get_version(0) == 0x50200)
118 out_le32(eddrtqcr1, 0x63b30002);
124 * This erratum requires a register write before being Memory
125 * controller 3 being enabled.
127 static void erratum_a008514(void)
129 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
132 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
133 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
134 out_le32(eddrtqcr1, 0x63b20002);
138 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
139 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
141 static unsigned long get_internval_val_mhz(void)
143 char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
145 * interval is the number of platform cycles(MHz) between
146 * wake up events generated by EPU.
148 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
151 interval_mhz = simple_strtoul(interval, NULL, 10);
156 void erratum_a009635(void)
159 unsigned long interval_mhz = get_internval_val_mhz();
164 val = in_le32(DCSR_CGACRE5);
165 writel(val | 0x00000200, DCSR_CGACRE5);
167 val = in_le32(EPU_EPCMPR5);
168 writel(interval_mhz, EPU_EPCMPR5);
169 val = in_le32(EPU_EPCCR5);
170 writel(val | 0x82820000, EPU_EPCCR5);
171 val = in_le32(EPU_EPSMCR5);
172 writel(val | 0x002f0000, EPU_EPSMCR5);
173 val = in_le32(EPU_EPECR5);
174 writel(val | 0x20000000, EPU_EPECR5);
175 val = in_le32(EPU_EPGCR);
176 writel(val | 0x80000000, EPU_EPGCR);
178 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
180 static void erratum_rcw_src(void)
182 #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
183 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
184 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
187 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
188 val &= ~DCFG_PORSR1_RCW_SRC;
189 val |= DCFG_PORSR1_RCW_SRC_NOR;
190 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
194 #define I2C_DEBUG_REG 0x6
195 #define I2C_GLITCH_EN 0x8
197 * This erratum requires setting glitch_en bit to enable
198 * digital glitch filter to improve clock stability.
200 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
201 static void erratum_a009203(void)
204 #ifdef CONFIG_SYS_I2C
205 #ifdef I2C1_BASE_ADDR
206 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
208 writeb(I2C_GLITCH_EN, ptr);
210 #ifdef I2C2_BASE_ADDR
211 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
213 writeb(I2C_GLITCH_EN, ptr);
215 #ifdef I2C3_BASE_ADDR
216 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
218 writeb(I2C_GLITCH_EN, ptr);
220 #ifdef I2C4_BASE_ADDR
221 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
223 writeb(I2C_GLITCH_EN, ptr);
229 void bypass_smmu(void)
232 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
233 out_le32(SMMU_SCR0, val);
234 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
235 out_le32(SMMU_NSCR0, val);
237 void fsl_lsch3_early_init_f(void)
240 init_early_memctl_regs(); /* tighten IFC timing */
241 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
248 #ifdef CONFIG_CHAIN_OF_TRUST
249 /* In case of Secure Boot, the IBR configures the SMMU
250 * to allow only Secure transactions.
251 * SMMU must be reset in bypass mode.
252 * Set the ClientPD bit and Clear the USFCFG Bit
254 if (fsl_check_boot_mode_secure() == 1)
259 #ifdef CONFIG_SCSI_AHCI_PLAT
262 struct ccsr_ahci __iomem *ccsr_ahci;
264 ccsr_ahci = (void *)CONFIG_SYS_SATA2;
265 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
266 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
267 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
269 ccsr_ahci = (void *)CONFIG_SYS_SATA1;
270 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
271 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
272 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
274 ahci_init((void __iomem *)CONFIG_SYS_SATA1);
281 #elif defined(CONFIG_FSL_LSCH2)
282 #ifdef CONFIG_SCSI_AHCI_PLAT
285 struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
287 /* Disable SATA ECC */
288 out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
289 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
290 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
291 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
293 ahci_init((void __iomem *)CONFIG_SYS_SATA);
300 static void erratum_a009929(void)
302 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
303 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
304 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
305 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
307 rstrqmr1 |= 0x00000400;
308 gur_out32(&gur->rstrqmr1, rstrqmr1);
309 writel(0x01000000, dcsr_cop_ccp);
314 * This erratum requires setting a value to eddrtqcr1 to optimal
315 * the DDR performance. The eddrtqcr1 register is in SCFG space
316 * of LS1043A and the offset is 0x157_020c.
318 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
319 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
320 #error A009660 and A008514 can not be both enabled.
323 static void erratum_a009660(void)
325 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
326 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
327 out_be32(eddrtqcr1, 0x63b20042);
331 static void erratum_a008850_early(void)
333 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
335 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
336 CONFIG_SYS_CCI400_OFFSET);
337 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
339 /* Skip if running at lower exception level */
340 if (current_el() < 3)
343 /* disables propagation of barrier transactions to DDRC from CCI400 */
344 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
346 /* disable the re-ordering in DDRC */
347 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
351 void erratum_a008850_post(void)
353 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
355 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
356 CONFIG_SYS_CCI400_OFFSET);
357 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
360 /* Skip if running at lower exception level */
361 if (current_el() < 3)
364 /* enable propagation of barrier transactions to DDRC from CCI400 */
365 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
367 /* enable the re-ordering in DDRC */
368 tmp = ddr_in32(&ddr->eor);
369 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
370 ddr_out32(&ddr->eor, tmp);
374 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
375 void erratum_a010315(void)
379 for (i = PCIE1; i <= PCIE4; i++)
380 if (!is_serdes_configured(i)) {
381 debug("PCIe%d: disabled all R/W permission!\n", i);
382 set_pcie_ns_access(i, 0);
387 static void erratum_a010539(void)
389 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
390 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
393 porsr1 = in_be32(&gur->porsr1);
394 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
395 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
400 /* Get VDD in the unit mV from voltage ID */
401 int get_core_volt_from_fuse(void)
403 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
408 fusesr = in_be32(&gur->dcfg_fusesr);
409 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
410 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
411 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
412 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
413 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
414 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
416 debug("%s: VID = 0x%x\n", __func__, vid);
418 case 0x00: /* VID isn't supported */
420 debug("%s: The VID feature is not supported\n", __func__);
422 case 0x08: /* 0.9V silicon */
425 case 0x10: /* 1.0V silicon */
428 default: /* Other core voltage */
430 printf("%s: The VID(%x) isn't supported\n", __func__, vid);
433 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
438 __weak int board_switch_core_volt(u32 vdd)
443 static int setup_core_volt(u32 vdd)
445 return board_setup_core_volt(vdd);
448 #ifdef CONFIG_SYS_FSL_DDR
449 static void ddr_enable_0v9_volt(bool en)
451 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
454 tmp = ddr_in32(&ddr->ddr_cdr1);
457 tmp |= DDR_CDR1_V0PT9_EN;
459 tmp &= ~DDR_CDR1_V0PT9_EN;
461 ddr_out32(&ddr->ddr_cdr1, tmp);
465 int setup_chip_volt(void)
469 vdd = get_core_volt_from_fuse();
470 /* Nothing to do for silicons doesn't support VID */
474 if (setup_core_volt(vdd))
475 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
476 #ifdef CONFIG_SYS_HAS_SERDES
477 if (setup_serdes_volt(vdd))
478 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
481 #ifdef CONFIG_SYS_FSL_DDR
483 ddr_enable_0v9_volt(true);
489 void fsl_lsch2_early_init_f(void)
491 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
492 CONFIG_SYS_CCI400_OFFSET);
493 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
495 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
496 enable_layerscape_ns_access();
499 #ifdef CONFIG_FSL_IFC
500 init_early_memctl_regs(); /* tighten IFC timing */
503 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
504 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
506 /* Make SEC reads and writes snoopable */
507 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
508 SCFG_SNPCNFGCR_SECWRSNP |
509 SCFG_SNPCNFGCR_SATARDSNP |
510 SCFG_SNPCNFGCR_SATAWRSNP);
513 * Enable snoop requests and DVM message requests for
514 * Slave insterface S4 (A53 core cluster)
516 if (current_el() == 3) {
517 out_le32(&cci->slave[4].snoop_ctrl,
518 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
522 erratum_a008850_early(); /* part 1 of 2 */
531 #ifdef CONFIG_QSPI_AHB_INIT
532 /* Enable 4bytes address support and fast read */
533 int qspi_ahb_init(void)
535 u32 *qspi_lut, lut_key, *qspi_key;
537 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
538 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
540 lut_key = in_be32(qspi_key);
542 if (lut_key == 0x5af05af0) {
543 /* That means the register is BE */
544 out_be32(qspi_key, 0x5af05af0);
545 /* Unlock the lut table */
546 out_be32(qspi_key + 1, 0x00000002);
547 out_be32(qspi_lut, 0x0820040c);
548 out_be32(qspi_lut + 1, 0x1c080c08);
549 out_be32(qspi_lut + 2, 0x00002400);
550 /* Lock the lut table */
551 out_be32(qspi_key, 0x5af05af0);
552 out_be32(qspi_key + 1, 0x00000001);
554 /* That means the register is LE */
555 out_le32(qspi_key, 0x5af05af0);
556 /* Unlock the lut table */
557 out_le32(qspi_key + 1, 0x00000002);
558 out_le32(qspi_lut, 0x0820040c);
559 out_le32(qspi_lut + 1, 0x1c080c08);
560 out_le32(qspi_lut + 2, 0x00002400);
561 /* Lock the lut table */
562 out_le32(qspi_key, 0x5af05af0);
563 out_le32(qspi_key + 1, 0x00000001);
570 #ifdef CONFIG_BOARD_LATE_INIT
571 int board_late_init(void)
573 #ifdef CONFIG_SCSI_AHCI_PLAT
576 #ifdef CONFIG_CHAIN_OF_TRUST
577 fsl_setenv_chain_of_trust();
579 #ifdef CONFIG_QSPI_AHB_INIT