1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014-2015 Freescale Semiconductor
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/soc.h>
14 #include <asm/global_data.h>
15 #include <asm/arch-fsl-layerscape/config.h>
16 #include <asm/arch-fsl-layerscape/ns_access.h>
17 #include <asm/arch-fsl-layerscape/fsl_icid.h>
18 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
21 #ifdef CONFIG_SYS_FSL_DDR
22 #include <fsl_ddr_sdram.h>
25 #ifdef CONFIG_CHAIN_OF_TRUST
26 #include <fsl_validate.h>
28 #include <fsl_immap.h>
30 #include <env_internal.h>
31 DECLARE_GLOBAL_DATA_PTR;
34 bool soc_has_dp_ddr(void)
36 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
37 u32 svr = gur_in32(&gur->svr);
39 /* LS2085A, LS2088A, LS2048A has DP_DDR */
40 if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
41 (SVR_SOC_VER(svr) == SVR_LS2088A) ||
42 (SVR_SOC_VER(svr) == SVR_LS2048A))
48 bool soc_has_aiop(void)
50 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
51 u32 svr = gur_in32(&gur->svr);
53 /* LS2085A has AIOP */
54 if (SVR_SOC_VER(svr) == SVR_LS2085A)
60 static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
62 scfg_clrsetbits32(scfg + offset / 4,
64 SCFG_USB_TXVREFTUNE << 6);
67 static void erratum_a009008(void)
69 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
70 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
72 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
73 defined(CONFIG_ARCH_LS1012A)
74 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
75 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
76 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
77 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
79 #elif defined(CONFIG_ARCH_LS2080A)
80 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
82 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
85 static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
87 scfg_clrbits32(scfg + offset / 4,
88 SCFG_USB_SQRXTUNE_MASK << 23);
91 static void erratum_a009798(void)
93 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
94 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
96 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
97 defined(CONFIG_ARCH_LS1012A)
98 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
99 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
100 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
101 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
103 #elif defined(CONFIG_ARCH_LS2080A)
104 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
106 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
109 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
110 defined(CONFIG_ARCH_LS1012A)
111 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
113 scfg_clrsetbits32(scfg + offset / 4,
115 SCFG_USB_PCSTXSWINGFULL << 9);
119 static void erratum_a008997(void)
121 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
122 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
123 defined(CONFIG_ARCH_LS1012A)
124 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
126 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
127 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
128 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
129 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
131 #elif defined(CONFIG_ARCH_LS1028A)
132 clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
134 DCSR_USB_PCSTXSWINGFULL << 11);
136 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
139 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
140 defined(CONFIG_ARCH_LS1012A)
142 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
143 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
144 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
145 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
146 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
148 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
149 defined(CONFIG_ARCH_LS1028A)
151 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
152 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
153 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
154 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
155 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
159 static void erratum_a009007(void)
161 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
162 defined(CONFIG_ARCH_LS1012A)
163 void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
165 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
166 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
167 usb_phy = (void __iomem *)SCFG_USB_PHY2;
168 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
170 usb_phy = (void __iomem *)SCFG_USB_PHY3;
171 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
173 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
174 defined(CONFIG_ARCH_LS1028A)
175 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
177 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
178 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
179 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
182 #if defined(CONFIG_FSL_LSCH3)
184 * This erratum requires setting a value to eddrtqcr1 to
185 * optimal the DDR performance.
187 static void erratum_a008336(void)
189 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
192 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
193 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
194 if (fsl_ddr_get_version(0) == 0x50200)
195 out_le32(eddrtqcr1, 0x63b30002);
197 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
198 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
199 if (fsl_ddr_get_version(0) == 0x50200)
200 out_le32(eddrtqcr1, 0x63b30002);
206 * This erratum requires a register write before being Memory
207 * controller 3 being enabled.
209 static void erratum_a008514(void)
211 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
214 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
215 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
216 out_le32(eddrtqcr1, 0x63b20002);
220 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
221 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
223 static unsigned long get_internval_val_mhz(void)
225 char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
227 * interval is the number of platform cycles(MHz) between
228 * wake up events generated by EPU.
230 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
233 interval_mhz = simple_strtoul(interval, NULL, 10);
238 void erratum_a009635(void)
241 unsigned long interval_mhz = get_internval_val_mhz();
246 val = in_le32(DCSR_CGACRE5);
247 writel(val | 0x00000200, DCSR_CGACRE5);
249 val = in_le32(EPU_EPCMPR5);
250 writel(interval_mhz, EPU_EPCMPR5);
251 val = in_le32(EPU_EPCCR5);
252 writel(val | 0x82820000, EPU_EPCCR5);
253 val = in_le32(EPU_EPSMCR5);
254 writel(val | 0x002f0000, EPU_EPSMCR5);
255 val = in_le32(EPU_EPECR5);
256 writel(val | 0x20000000, EPU_EPECR5);
257 val = in_le32(EPU_EPGCR);
258 writel(val | 0x80000000, EPU_EPGCR);
260 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
262 static void erratum_rcw_src(void)
264 #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
265 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
266 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
269 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
270 val &= ~DCFG_PORSR1_RCW_SRC;
271 val |= DCFG_PORSR1_RCW_SRC_NOR;
272 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
276 #define I2C_DEBUG_REG 0x6
277 #define I2C_GLITCH_EN 0x8
279 * This erratum requires setting glitch_en bit to enable
280 * digital glitch filter to improve clock stability.
282 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
283 static void erratum_a009203(void)
285 #ifdef CONFIG_SYS_I2C
287 #ifdef I2C1_BASE_ADDR
288 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
290 writeb(I2C_GLITCH_EN, ptr);
292 #ifdef I2C2_BASE_ADDR
293 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
295 writeb(I2C_GLITCH_EN, ptr);
297 #ifdef I2C3_BASE_ADDR
298 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
300 writeb(I2C_GLITCH_EN, ptr);
302 #ifdef I2C4_BASE_ADDR
303 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
305 writeb(I2C_GLITCH_EN, ptr);
311 void bypass_smmu(void)
314 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
315 out_le32(SMMU_SCR0, val);
316 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
317 out_le32(SMMU_NSCR0, val);
319 void fsl_lsch3_early_init_f(void)
322 #ifdef CONFIG_FSL_IFC
323 init_early_memctl_regs(); /* tighten IFC timing */
325 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
334 #ifdef CONFIG_CHAIN_OF_TRUST
335 /* In case of Secure Boot, the IBR configures the SMMU
336 * to allow only Secure transactions.
337 * SMMU must be reset in bypass mode.
338 * Set the ClientPD bit and Clear the USFCFG Bit
340 if (fsl_check_boot_mode_secure() == 1)
344 #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
349 /* Get VDD in the unit mV from voltage ID */
350 int get_core_volt_from_fuse(void)
352 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
357 /* get the voltage ID from fuse status register */
358 fusesr = in_le32(&gur->dcfg_fusesr);
359 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
360 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
361 FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
362 if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
363 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
364 FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
366 debug("%s: VID = 0x%x\n", __func__, vid);
368 case 0x00: /* VID isn't supported */
370 debug("%s: The VID feature is not supported\n", __func__);
372 case 0x08: /* 0.9V silicon */
375 case 0x10: /* 1.0V silicon */
378 default: /* Other core voltage */
380 debug("%s: The VID(%x) isn't supported\n", __func__, vid);
383 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
388 #elif defined(CONFIG_FSL_LSCH2)
390 static void erratum_a009929(void)
392 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
393 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
394 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
395 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
397 rstrqmr1 |= 0x00000400;
398 gur_out32(&gur->rstrqmr1, rstrqmr1);
399 writel(0x01000000, dcsr_cop_ccp);
404 * This erratum requires setting a value to eddrtqcr1 to optimal
405 * the DDR performance. The eddrtqcr1 register is in SCFG space
406 * of LS1043A and the offset is 0x157_020c.
408 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
409 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
410 #error A009660 and A008514 can not be both enabled.
413 static void erratum_a009660(void)
415 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
416 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
417 out_be32(eddrtqcr1, 0x63b20042);
421 static void erratum_a008850_early(void)
423 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
425 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
426 CONFIG_SYS_CCI400_OFFSET);
427 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
429 /* Skip if running at lower exception level */
430 if (current_el() < 3)
433 /* disables propagation of barrier transactions to DDRC from CCI400 */
434 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
436 /* disable the re-ordering in DDRC */
437 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
441 void erratum_a008850_post(void)
443 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
445 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
446 CONFIG_SYS_CCI400_OFFSET);
447 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
450 /* Skip if running at lower exception level */
451 if (current_el() < 3)
454 /* enable propagation of barrier transactions to DDRC from CCI400 */
455 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
457 /* enable the re-ordering in DDRC */
458 tmp = ddr_in32(&ddr->eor);
459 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
460 ddr_out32(&ddr->eor, tmp);
464 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
465 void erratum_a010315(void)
469 for (i = PCIE1; i <= PCIE4; i++)
470 if (!is_serdes_configured(i)) {
471 debug("PCIe%d: disabled all R/W permission!\n", i);
472 set_pcie_ns_access(i, 0);
477 static void erratum_a010539(void)
479 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
480 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
483 porsr1 = in_be32(&gur->porsr1);
484 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
485 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
487 out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
491 /* Get VDD in the unit mV from voltage ID */
492 int get_core_volt_from_fuse(void)
494 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
499 fusesr = in_be32(&gur->dcfg_fusesr);
500 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
501 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
502 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
503 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
504 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
505 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
507 debug("%s: VID = 0x%x\n", __func__, vid);
509 case 0x00: /* VID isn't supported */
511 debug("%s: The VID feature is not supported\n", __func__);
513 case 0x08: /* 0.9V silicon */
516 case 0x10: /* 1.0V silicon */
519 default: /* Other core voltage */
521 printf("%s: The VID(%x) isn't supported\n", __func__, vid);
524 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
529 __weak int board_switch_core_volt(u32 vdd)
534 static int setup_core_volt(u32 vdd)
536 return board_setup_core_volt(vdd);
539 #ifdef CONFIG_SYS_FSL_DDR
540 static void ddr_enable_0v9_volt(bool en)
542 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
545 tmp = ddr_in32(&ddr->ddr_cdr1);
548 tmp |= DDR_CDR1_V0PT9_EN;
550 tmp &= ~DDR_CDR1_V0PT9_EN;
552 ddr_out32(&ddr->ddr_cdr1, tmp);
556 int setup_chip_volt(void)
560 vdd = get_core_volt_from_fuse();
561 /* Nothing to do for silicons doesn't support VID */
565 if (setup_core_volt(vdd))
566 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
567 #ifdef CONFIG_SYS_HAS_SERDES
568 if (setup_serdes_volt(vdd))
569 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
572 #ifdef CONFIG_SYS_FSL_DDR
574 ddr_enable_0v9_volt(true);
580 #ifdef CONFIG_FSL_PFE
581 void init_pfe_scfg_dcfg_regs(void)
583 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
586 out_be32(&scfg->pfeasbcr,
587 in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
588 out_be32(&scfg->pfebsbcr,
589 in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
591 /* CCI-400 QoS settings for PFE */
592 out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
593 | SCFG_WR_QOS1_PFE2_QOS));
594 out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
595 | SCFG_RD_QOS1_PFE2_QOS));
597 ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
598 out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
599 ecccr2 | (unsigned int)DISABLE_PFE_ECC);
603 void fsl_lsch2_early_init_f(void)
605 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
606 CONFIG_SYS_CCI400_OFFSET);
607 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
608 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
612 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
613 enable_layerscape_ns_access();
616 #ifdef CONFIG_FSL_IFC
617 init_early_memctl_regs(); /* tighten IFC timing */
620 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
621 src = get_boot_src();
622 if (src != BOOT_SOURCE_QSPI_NOR)
623 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
625 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
626 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
629 /* Make SEC reads and writes snoopable */
630 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
631 SCFG_SNPCNFGCR_SECWRSNP |
632 SCFG_SNPCNFGCR_SATARDSNP |
633 SCFG_SNPCNFGCR_SATAWRSNP);
636 * Enable snoop requests and DVM message requests for
637 * Slave insterface S4 (A53 core cluster)
639 if (current_el() == 3) {
640 out_le32(&cci->slave[4].snoop_ctrl,
641 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
645 * Program Central Security Unit (CSU) to grant access
646 * permission for USB 2.0 controller
648 #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
649 if (current_el() == 3)
650 set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
653 erratum_a008850_early(); /* part 1 of 2 */
662 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
668 #ifdef CONFIG_QSPI_AHB_INIT
669 /* Enable 4bytes address support and fast read */
670 int qspi_ahb_init(void)
672 u32 *qspi_lut, lut_key, *qspi_key;
674 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
675 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
677 lut_key = in_be32(qspi_key);
679 if (lut_key == 0x5af05af0) {
680 /* That means the register is BE */
681 out_be32(qspi_key, 0x5af05af0);
682 /* Unlock the lut table */
683 out_be32(qspi_key + 1, 0x00000002);
684 out_be32(qspi_lut, 0x0820040c);
685 out_be32(qspi_lut + 1, 0x1c080c08);
686 out_be32(qspi_lut + 2, 0x00002400);
687 /* Lock the lut table */
688 out_be32(qspi_key, 0x5af05af0);
689 out_be32(qspi_key + 1, 0x00000001);
691 /* That means the register is LE */
692 out_le32(qspi_key, 0x5af05af0);
693 /* Unlock the lut table */
694 out_le32(qspi_key + 1, 0x00000002);
695 out_le32(qspi_lut, 0x0820040c);
696 out_le32(qspi_lut + 1, 0x1c080c08);
697 out_le32(qspi_lut + 2, 0x00002400);
698 /* Lock the lut table */
699 out_le32(qspi_key, 0x5af05af0);
700 out_le32(qspi_key + 1, 0x00000001);
707 #ifdef CONFIG_TFABOOT
708 #define MAX_BOOTCMD_SIZE 512
710 int fsl_setenv_bootcmd(void)
713 enum boot_src src = get_boot_src();
714 char bootcmd_str[MAX_BOOTCMD_SIZE];
717 #ifdef IFC_NOR_BOOTCOMMAND
718 case BOOT_SOURCE_IFC_NOR:
719 sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
722 #ifdef QSPI_NOR_BOOTCOMMAND
723 case BOOT_SOURCE_QSPI_NOR:
724 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
727 #ifdef XSPI_NOR_BOOTCOMMAND
728 case BOOT_SOURCE_XSPI_NOR:
729 sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
732 #ifdef IFC_NAND_BOOTCOMMAND
733 case BOOT_SOURCE_IFC_NAND:
734 sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
737 #ifdef QSPI_NAND_BOOTCOMMAND
738 case BOOT_SOURCE_QSPI_NAND:
739 sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
742 #ifdef XSPI_NAND_BOOTCOMMAND
743 case BOOT_SOURCE_XSPI_NAND:
744 sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
747 #ifdef SD_BOOTCOMMAND
748 case BOOT_SOURCE_SD_MMC:
749 sprintf(bootcmd_str, SD_BOOTCOMMAND);
752 #ifdef SD2_BOOTCOMMAND
753 case BOOT_SOURCE_SD_MMC2:
754 sprintf(bootcmd_str, SD2_BOOTCOMMAND);
758 #ifdef QSPI_NOR_BOOTCOMMAND
759 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
764 ret = env_set("bootcmd", bootcmd_str);
766 printf("Failed to set bootcmd: ret = %d\n", ret);
772 int fsl_setenv_mcinitcmd(void)
775 enum boot_src src = get_boot_src();
778 #ifdef IFC_MC_INIT_CMD
779 case BOOT_SOURCE_IFC_NAND:
780 case BOOT_SOURCE_IFC_NOR:
781 ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
784 #ifdef QSPI_MC_INIT_CMD
785 case BOOT_SOURCE_QSPI_NAND:
786 case BOOT_SOURCE_QSPI_NOR:
787 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
790 #ifdef XSPI_MC_INIT_CMD
791 case BOOT_SOURCE_XSPI_NAND:
792 case BOOT_SOURCE_XSPI_NOR:
793 ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
796 #ifdef SD_MC_INIT_CMD
797 case BOOT_SOURCE_SD_MMC:
798 ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
801 #ifdef SD2_MC_INIT_CMD
802 case BOOT_SOURCE_SD_MMC2:
803 ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
807 #ifdef QSPI_MC_INIT_CMD
808 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
814 printf("Failed to set mcinitcmd: ret = %d\n", ret);
821 #ifdef CONFIG_BOARD_LATE_INIT
822 int board_late_init(void)
824 #ifdef CONFIG_CHAIN_OF_TRUST
825 fsl_setenv_chain_of_trust();
827 #ifdef CONFIG_TFABOOT
829 * check if gd->env_addr is default_environment; then setenv bootcmd
832 #if !defined(CONFIG_ENV_ADDR) || defined(ENV_IS_EMBEDDED)
833 if (gd->env_addr == (ulong)&default_environment[0]) {
835 if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
837 fsl_setenv_bootcmd();
838 fsl_setenv_mcinitcmd();
842 * If the boot mode is secure, default environment is not present then
843 * setenv command needs to be run by default
845 #ifdef CONFIG_CHAIN_OF_TRUST
846 if ((fsl_check_boot_mode_secure() == 1)) {
847 fsl_setenv_bootcmd();
848 fsl_setenv_mcinitcmd();
852 #ifdef CONFIG_QSPI_AHB_INIT