arch/arm/cpu/armv8/fsl-layerscape/mp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <asm/cache.h>
   9 #include <asm/io.h>
  10 #include <asm/system.h>
  11 #include <asm/arch/mp.h>
  12 #include <asm/arch/soc.h>
  13 #include "cpu.h"
  14 #include <asm/arch-fsl-layerscape/soc.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 void *get_spin_tbl_addr(void)
  19 {
  20         return &__spin_table;
  21 }
  22
  23 phys_addr_t determine_mp_bootpg(void)
  24 {
  25         return (phys_addr_t)&secondary_boot_code;
  26 }
  27
  28 void update_os_arch_secondary_cores(uint8_t os_arch)
  29 {
  30         u64 *table = get_spin_tbl_addr();
  31         int i;
  32
  33         for (i = 1; i < CONFIG_MAX_CPUS; i++) {
  34                 if (os_arch == IH_ARCH_DEFAULT)
  35                         table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  36                                 SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_SAME;
  37                 else
  38                         table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  39                                 SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_DIFF;
  40         }
  41 }
  42
  43 #ifdef CONFIG_FSL_LSCH3
  44 void wake_secondary_core_n(int cluster, int core, int cluster_cores)
  45 {
  46         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  47         struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
  48         u32 mpidr = 0;
  49
  50         mpidr = ((cluster << 8) | core);
  51         /*
  52          * mpidr_el1 register value of core which needs to be released
  53          * is written to scratchrw[6] register
  54          */
  55         gur_out32(&gur->scratchrw[6], mpidr);
  56         asm volatile("dsb st" : : : "memory");
  57         rst->brrl |= 1 << ((cluster * cluster_cores) + core);
  58         asm volatile("dsb st" : : : "memory");
  59         /*
  60          * scratchrw[6] register value is polled
  61          * when the value becomes zero, this means that this core is up
  62          * and running, next core can be released now
  63          */
  64         while (gur_in32(&gur->scratchrw[6]) != 0)
  65                 ;
  66 }
  67 #endif
  68
  69 int fsl_layerscape_wake_seconday_cores(void)
  70 {
  71         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  72 #ifdef CONFIG_FSL_LSCH3
  73         struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
  74         u32 svr, ver, cluster, type;
  75         int j = 0, cluster_cores = 0;
  76 #elif defined(CONFIG_FSL_LSCH2)
  77         struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
  78 #endif
  79         u32 cores, cpu_up_mask = 1;
  80         int i, timeout = 10;
  81         u64 *table = get_spin_tbl_addr();
  82
  83 #ifdef COUNTER_FREQUENCY_REAL
  84         /* update for secondary cores */
  85         __real_cntfrq = COUNTER_FREQUENCY_REAL;
  86         flush_dcache_range((unsigned long)&__real_cntfrq,
  87                            (unsigned long)&__real_cntfrq + 8);
  88 #endif
  89
  90         cores = cpu_mask();
  91         /* Clear spin table so that secondary processors
  92          * observe the correct value after waking up from wfe.
  93          */
  94         memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE);
  95         flush_dcache_range((unsigned long)table,
  96                            (unsigned long)table +
  97                            (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
  98
  99         printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
 100
 101 #ifdef CONFIG_FSL_LSCH3
 102         gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
 103         gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
 104
 105         svr = gur_in32(&gur->svr);
 106         ver = SVR_SOC_VER(svr);
 107         if (ver == SVR_LS2080A || ver == SVR_LS2085A) {
 108                 gur_out32(&gur->scratchrw[6], 1);
 109                 asm volatile("dsb st" : : : "memory");
 110                 rst->brrl = cores;
 111                 asm volatile("dsb st" : : : "memory");
 112         } else {
 113                 /*
 114                  * Release the cores out of reset one-at-a-time to avoid
 115                  * power spikes
 116                  */
 117                 i = 0;
 118                 cluster = in_le32(&gur->tp_cluster[i].lower);
 119                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 120                         type = initiator_type(cluster, j);
 121                         if (type &&
 122                             TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 123                                 cluster_cores++;
 124                 }
 125
 126                 do {
 127                         cluster = in_le32(&gur->tp_cluster[i].lower);
 128                         for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 129                                 type = initiator_type(cluster, j);
 130                                 if (type &&
 131                                     TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 132                                         wake_secondary_core_n(i, j,
 133                                                               cluster_cores);
 134                         }
 135                 i++;
 136                 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
 137         }
 138 #elif defined(CONFIG_FSL_LSCH2)
 139         scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
 140         scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
 141         asm volatile("dsb st" : : : "memory");
 142         gur_out32(&gur->brrl, cores);
 143         asm volatile("dsb st" : : : "memory");
 144
 145         /* Bootup online cores */
 146         scfg_out32(&scfg->corebcr, cores);
 147 #endif
 148         /* This is needed as a precautionary measure.
 149          * If some code before this has accidentally  released the secondary
 150          * cores then the pre-bootloader code will trap them in a "wfe" unless
 151          * the scratchrw[6] is set. In this case we need a sev here to get these
 152          * cores moving again.
 153          */
 154         asm volatile("sev");
 155
 156         while (timeout--) {
 157                 flush_dcache_range((unsigned long)table, (unsigned long)table +
 158                                    CONFIG_MAX_CPUS * 64);
 159                 for (i = 1; i < CONFIG_MAX_CPUS; i++) {
 160                         if (table[i * WORDS_PER_SPIN_TABLE_ENTRY +
 161                                         SPIN_TABLE_ELEM_STATUS_IDX])
 162                                 cpu_up_mask |= 1 << i;
 163                 }
 164                 if (hweight32(cpu_up_mask) == hweight32(cores))
 165                         break;
 166                 udelay(10);
 167         }
 168         if (timeout <= 0) {
 169                 printf("Not all cores (0x%x) are up (0x%x)\n",
 170                        cores, cpu_up_mask);
 171                 return 1;
 172         }
 173         printf("All (%d) cores are up.\n", hweight32(cores));
 174
 175         return 0;
 176 }
 177
 178 int is_core_valid(unsigned int core)
 179 {
 180         return !!((1 << core) & cpu_mask());
 181 }
 182
 183 static int is_pos_valid(unsigned int pos)
 184 {
 185         return !!((1 << pos) & cpu_pos_mask());
 186 }
 187
 188 int is_core_online(u64 cpu_id)
 189 {
 190         u64 *table;
 191         int pos = id_to_core(cpu_id);
 192         table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY;
 193         return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
 194 }
 195
 196 int cpu_reset(u32 nr)
 197 {
 198         puts("Feature is not implemented.\n");
 199
 200         return 0;
 201 }
 202
 203 int cpu_disable(u32 nr)
 204 {
 205         puts("Feature is not implemented.\n");
 206
 207         return 0;
 208 }
 209
 210 static int core_to_pos(int nr)
 211 {
 212         u32 cores = cpu_pos_mask();
 213         int i, count = 0;
 214
 215         if (nr == 0) {
 216                 return 0;
 217         } else if (nr >= hweight32(cores)) {
 218                 puts("Not a valid core number.\n");
 219                 return -1;
 220         }
 221
 222         for (i = 1; i < 32; i++) {
 223                 if (is_pos_valid(i)) {
 224                         count++;
 225                         if (count == nr)
 226                                 break;
 227                 }
 228         }
 229
 230         if (count != nr)
 231                 return -1;
 232
 233         return i;
 234 }
 235
 236 int cpu_status(u32 nr)
 237 {
 238         u64 *table;
 239         int pos;
 240
 241         if (nr == 0) {
 242                 table = (u64 *)get_spin_tbl_addr();
 243                 printf("table base @ 0x%p\n", table);
 244         } else {
 245                 pos = core_to_pos(nr);
 246                 if (pos < 0)
 247                         return -1;
 248                 table = (u64 *)get_spin_tbl_addr() + pos *
 249                         WORDS_PER_SPIN_TABLE_ENTRY;
 250                 printf("table @ 0x%p\n", table);
 251                 printf("   addr - 0x%016llx\n",
 252                        table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]);
 253                 printf("   status   - 0x%016llx\n",
 254                        table[SPIN_TABLE_ELEM_STATUS_IDX]);
 255                 printf("   lpid  - 0x%016llx\n",
 256                        table[SPIN_TABLE_ELEM_LPID_IDX]);
 257         }
 258
 259         return 0;
 260 }
 261
 262 int cpu_release(u32 nr, int argc, char * const argv[])
 263 {
 264         u64 boot_addr;
 265         u64 *table = (u64 *)get_spin_tbl_addr();
 266         int pos;
 267
 268         pos = core_to_pos(nr);
 269         if (pos <= 0)
 270                 return -1;
 271
 272         table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
 273         boot_addr = simple_strtoull(argv[0], NULL, 16);
 274         table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
 275         flush_dcache_range((unsigned long)table,
 276                            (unsigned long)table + SPIN_TABLE_ELEM_SIZE);
 277         asm volatile("dsb st");
 278         smp_kick_all_cpus();    /* only those with entry addr set will run */
 279         /*
 280          * When the first release command runs, all cores are set to go. Those
 281          * without a valid entry address will be trapped by "wfe". "sev" kicks
 282          * them off to check the address again. When set, they continue to run.
 283          */
 284         asm volatile("sev");
 285
 286         return 0;
 287 }