1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor, Inc.
7 #include <asm/arch/fsl_serdes.h>
8 #include <asm/arch/immap_lsch2.h>
10 struct serdes_config {
12 u8 lanes[SRDS_MAX_LANES];
15 static struct serdes_config serdes1_cfg_tbl[] = {
17 {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3} },
18 {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} },
19 {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3} },
20 {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA1} },
21 {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
22 {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
23 {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5,
25 {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
26 {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA1} },
27 {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} },
28 {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA1} },
29 {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1} },
30 {0x9998, {PCIE1, PCIE2, PCIE3, SATA1} },
31 {0x6058, {PCIE1, PCIE1, PCIE2, SATA1} },
32 {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3} },
33 {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3} },
34 {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3} },
35 {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5,
40 static struct serdes_config *serdes_cfg_tbl[] = {
44 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
46 struct serdes_config *ptr;
48 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
51 ptr = serdes_cfg_tbl[serdes];
52 while (ptr->protocol) {
53 if (ptr->protocol == cfg)
54 return ptr->lanes[lane];
61 int is_serdes_prtcl_valid(int serdes, u32 prtcl)
64 struct serdes_config *ptr;
66 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
69 ptr = serdes_cfg_tbl[serdes];
70 while (ptr->protocol) {
71 if (ptr->protocol == prtcl)
79 for (i = 0; i < SRDS_MAX_LANES; i++) {
80 if (ptr->lanes[i] != NONE)