1 // SPDX-License-Identifier: GPL-2.0+
7 #include <asm/arch/fsl_serdes.h>
11 u8 lanes[SRDS_MAX_LANES];
12 u8 rcw_lanes[SRDS_MAX_LANES];
15 static struct serdes_config serdes1_cfg_tbl[] = {
17 {0xCC5B, {PCIE1, QSGMII_B, PCIE2, PCIE2} },
18 {0xEB99, {SGMII1, SGMII1, PCIE2, SATA1} },
19 {0xCC99, {SGMII1, SGMII1, PCIE2, PCIE2} },
20 {0xBB99, {SGMII1, SGMII1, PCIE2, PCIE1} },
21 {0x9999, {SGMII1, SGMII2, SGMII3, SGMII4} },
22 {0xEBCC, {PCIE1, PCIE1, PCIE2, SATA1} },
23 {0xCCCC, {PCIE1, PCIE1, PCIE2, PCIE2} },
24 {0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} },
25 {0xE031, {SXGMII1, QXGMII2, NONE, SATA1} },
26 {0xB991, {SXGMII1, SGMII1, SGMII2, PCIE1} },
27 {0xBB31, {SXGMII1, QXGMII2, PCIE2, PCIE1} },
28 {0xCC31, {SXGMII1, QXGMII2, PCIE2, PCIE2} },
29 {0xBB51, {SXGMII1, QSGMII_B, PCIE2, PCIE1} },
30 {0xBB38, {SGMII_T1, QXGMII2, PCIE2, PCIE1} },
31 {0xCC38, {SGMII_T1, QXGMII2, PCIE2, PCIE2} },
32 {0xBB58, {SGMII_T1, QSGMII_B, PCIE2, PCIE1} },
33 {0xCC58, {SGMII_T1, QSGMII_B, PCIE2, PCIE2} },
34 {0xCC8B, {PCIE1, SGMII_T1, PCIE2, PCIE2} },
35 {0xEB58, {SGMII_T1, QSGMII_B, PCIE2, SATA1} },
36 {0xEB8B, {PCIE1, SGMII_T1, PCIE2, SATA1} },
37 {0xE8CC, {PCIE1, PCIE1, SGMII_T1, SATA1} },
41 static struct serdes_config *serdes_cfg_tbl[] = {
45 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
47 struct serdes_config *ptr;
49 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
52 ptr = serdes_cfg_tbl[serdes];
53 while (ptr->protocol) {
54 if (ptr->protocol == cfg)
55 return ptr->lanes[lane];
62 int is_serdes_prtcl_valid(int serdes, u32 prtcl)
65 struct serdes_config *ptr;
67 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
70 ptr = serdes_cfg_tbl[serdes];
71 while (ptr->protocol) {
72 if (ptr->protocol == prtcl)
80 for (i = 0; i < SRDS_MAX_LANES; i++) {
81 if (ptr->lanes[i] != NONE)