arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
   8 #include <asm/arch-fsl-layerscape/fsl_icid.h>
   9 #include <asm/arch-fsl-layerscape/fsl_portals.h>
  10
  11 struct icid_id_table icid_tbl[] = {
  12         SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
  13         SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
  14         SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
  15         SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID),
  16         SET_SATA_ICID(1, "fsl,ls1028a-ahci", FSL_SATA1_STREAM_ID),
  17         SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
  18         SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
  19         SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
  20         SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
  21 #ifdef CONFIG_FSL_CAAM
  22         SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
  23         SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
  24         SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
  25         SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
  26         SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
  27         SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
  28         SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
  29         SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
  30         SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
  31         SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
  32 #endif
  33 };
  34
  35 int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
  36
  37 /* integrated PCI is handled separately as it's not part of CCSR/SCFG */
  38 #ifdef CONFIG_PCIE_ECAM_GENERIC
  39
  40 #define ECAM_IERB_BASE          0x1f0800000ULL
  41 #define ECAM_IERB_OFFSET_NA     -1
  42 #define ECAM_IERB_FUNC_CNT      ARRAY_SIZE(ierb_offset)
  43 /* cache related transaction attributes for PCIe functions */
  44 #define ECAM_IERB_MSICAR                (ECAM_IERB_BASE + 0xa400)
  45 #define ECAM_IERB_MSICAR_VALUE          0x30
  46
  47 /* offset of IERB config register per PCI function */
  48 static int ierb_offset[] = {
  49         0x0800,
  50         0x1800,
  51         0x2800,
  52         0x3800,
  53         0x4800,
  54         0x5800,
  55         0x6800,
  56         ECAM_IERB_OFFSET_NA,
  57         0x0804,
  58         0x0808,
  59         0x1804,
  60         0x1808,
  61 };
  62
  63 /*
  64  * Use a custom function for LS1028A, for now this is the only SoC with IERB
  65  * and we're currently considering reorganizing IERB for future SoCs.
  66  */
  67 void set_ecam_icids(void)
  68 {
  69         int i;
  70
  71         out_le32(ECAM_IERB_MSICAR, ECAM_IERB_MSICAR_VALUE);
  72
  73         for (i = 0; i < ECAM_IERB_FUNC_CNT; i++) {
  74                 if (ierb_offset[i] == ECAM_IERB_OFFSET_NA)
  75                         continue;
  76
  77                 out_le32(ECAM_IERB_BASE + ierb_offset[i],
  78                          FSL_ECAM_STREAM_ID_START + i);
  79         }
  80 }
  81
  82 static int fdt_setprop_inplace_idx_u32(void *fdt, int nodeoffset,
  83                                        const char *name, uint32_t idx, u32 val)
  84 {
  85         val = cpu_to_be32(val);
  86         return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name,
  87                                                    strlen(name),
  88                                                    idx * sizeof(val), &val,
  89                                                    sizeof(val));
  90 }
  91
  92 static int fdt_getprop_len(void *fdt, int nodeoffset, const char *name)
  93 {
  94         int len;
  95
  96         if (fdt_getprop_namelen(fdt, nodeoffset, name, strlen(name), &len))
  97                 return len;
  98
  99         return 0;
 100 }
 101
 102 void fdt_fixup_ecam(void *blob)
 103 {
 104         int off;
 105
 106         off = fdt_node_offset_by_compatible(blob, 0, "pci-host-ecam-generic");
 107         if (off < 0) {
 108                 debug("ECAM node not found\n");
 109                 return;
 110         }
 111
 112         if (fdt_getprop_len(blob, off, "msi-map") != 16 ||
 113             fdt_getprop_len(blob, off, "iommu-map") != 16) {
 114                 log_err("invalid msi/iommu-map propertly size in ECAM node\n");
 115                 return;
 116         }
 117
 118         fdt_setprop_inplace_idx_u32(blob, off, "msi-map", 2,
 119                                     FSL_ECAM_STREAM_ID_START);
 120         fdt_setprop_inplace_idx_u32(blob, off, "msi-map", 3,
 121                                     ECAM_IERB_FUNC_CNT);
 122
 123         fdt_setprop_inplace_idx_u32(blob, off, "iommu-map", 2,
 124                                     FSL_ECAM_STREAM_ID_START);
 125         fdt_setprop_inplace_idx_u32(blob, off, "iommu-map", 3,
 126                                     ECAM_IERB_FUNC_CNT);
 127 }
 128 #endif /* CONFIG_PCIE_ECAM_GENERIC */